• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.341-346
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• 2014

This paper has presented the design and fabrication of phase correlator for wideband digital frequency discriminator (DFD) operating over the 6.0 to 18.0 GHz frequency range. Fabricated DFD phase correlator has been measured I or Q output signal, and analyzed frequency discrimination error. The operation of the proposed mixer type correlator has been analyzed by deriving some analytic equations. To design the phase correlator, this paper has modeled and simulated IQ mixer and 8-way power divider by using RF simulation tool. Designed phase correlator has fabricated and measured. The phase error and frequency discrimination error have been presented using by measured I and Q output signal. Over the 6.0~18.0 GHz range, the root mean square(RMS) phase error is $4.81^{\circ}$, RMS and frequency discrimination error is 1.49 MHz, RMS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.214-217
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• 2001

This paper presents an implementation methodology of common Rf- integrated PCS base station system which, is capable of providing PCS services for 3 PCS carriers concurrently and wireless system performance evaluation data is shown. We have built up a common PCS base station system using a commonization module, which is consisted of a multi-channel combiner, duplexer, LNA, power divider, feeder line, and a common set of antennas. It was shown that the performance of the system within the total 30MHz PCS frequency range is uniformly acceptable and measured signal quality and coverage are equivalent to that of the individual PCS base station. It is expected that PCS carriers are able to save a huge amount of installation and maintenance expenses by installing and sharing this base station system. This paper forms a groundwork for deploying efficient and economical IMT-2000 network.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.99-102
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• 2012

An image scaler is a IP used in a image processing block of display devices to adjust image size. Proposed image scaler adopts line memories instead of a conventional method using a frame memory. This method reduced hardware resources and enhanced data precision by using shift operations that number is multiplied by $2^m$ and divided again at final stage for scaling. Also image scaler increased efficiency of IP by using serial divider to calculate parameters by itself. Parameters used in image scaling is automatically produced by it. Suggested methods are designed by Verilog HDL and implemented with Xilinx Vertex-4 XC4LX80 and ASIC using TSMC 0.18um process.

• The Journal of the Korea Contents Association
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• v.15 no.12
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• pp.1-7
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• 2015

These anti-jamming GPS systems are verified using large anechoic chamber or field-test until now. When using a large anechoic chamber, Independent verification from external enviroments like noise is an advantage but high cost and availability of chamber are disadvantages. And in case of field test, verification under real propagation enviroment is an advantage but security problem of military equipments and problem of making same test condition are disadvantages. This paper presents an newly developed anti-jamming GPS test system. This test system mainly consists of small anechoic chamber, jamming divider, jamming signal generator and satellite simulator. The small anechoic chamber is installed many jamming antennas to transmit multi jamming signals and the jamming divider is newly developed to control multi jamming signals. According to self performance test and combined test with Anti-jamming GPS receiver, we verified our system's reliability.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.2
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• pp.19-29
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• 2004

In this paper, the beam steering dipole phased array antenna systems for IMT-2000 base station have been designed. The designed beam steering dipole phased array antenna systems are constituted by the antenna part and the beam steering control system part. The antenna part is designed by the proposed flat dipole for the broadband characteristics, and the 8${\times}$8 dipole way antenna is constructed by the Proposed flat dipole for the directional radiation pattern. Besides the vertical Power divider is designed for the vertical power distribution. The beam steering control system part is designed the horizontal power divider for the horizontal power distribution, the 4-bit phase shifters and the driving circuit of phase shifters for the horizontal beam tilting. In order to evaluate a performance of the designed antenna systems, they were fabricated and the radiation characteristics were measured. From the measured results, we found that the horizontal beams were tilted by the each control signals, and the measured radiation characteristics showed good agreement with the design goals.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.125-130
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• 2011

In this paper, SIW-based $2{\times}4$ uniform array antenna with a sequentially fed 8-way power divider with an equal division characteristic is proposed for an application of X-band satellite communication. In particular, sequential feeding structures with a progressive phase difference of 90 degrees between the nearest elements have been suggested to protect the cancellation of electric fields due to the array alignments and to enhance the purity of RHCP(Right-Handed Circular Polarization). The obtained results according to the return loss bandwidth, RHCP antenna gain, axial ratio bandwidth are 760 MHz ranging from 7.90 to 8.66 GHz under the criterion of less than -10 dB, 14.3 dBic at 8.3 GHz, and 600 MHz from 8.15 to 8.75 GHz, respectively. In addition, it is observed that the equal-division characteristic of SIW-based 8-way power divider is approximately -9.2 dB in all ports.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.11
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• pp.978-986
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• 2016

X-band phased array antenna module for the compensation of deformed beam direction by wing deformation is designed and fabricated. The phased array antenna module consists of array antenna, phase shifter, power divider and control circuit. To select out the best component, the variation of radiation pattern by wing bending and phase error of components is simulated. The fabricated phased array antenna module shows an antenna gain of 5.84 dBi, a return loss of 13.6 dB and a bandwidth of 10.6 % at 9.375 GHz. The test bed was set up to verify the performance of beam direction compensation. This test confirmed that the main beam direction of array antenna has been well restored under wing bending of 9 %.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.35-40
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• 2008

This paper proposes a dual-band balun which is based on Wilkinson power divider. By inserting $\lambda/2$ transmission line between port 2 and 3, this balun shows good matching at all ports and improved isolation. We use matamaterial(CRLH, D-CRLH) structure for a miniaturization of the circuit implementation and dual-band operation at TDMB frequency range(195MHz) and DVB-H frequency range(670MHz). The proposed balun is designed with return loss larger than -12.98dB at all port, and isolation larger than -12.4dB, the amplitude imbalance between output signals less than 0.08dB, also phase differences of outputs less than $2.8^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.522-529
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• 2007

A semidynamic frequency divide-by-1.5 MMIC comprises a tunable polyphase filter, tunable image-rejection mixer, and a static divide-by-2 in the feedback path. Wideband suppression of unwanted tones is achieved by employing a tunable image-rejection mixer and a tunable single-stage polyphase filter. Implemented in GaInP/GaAs HBT technology, the divide-by-1.5 MMIC operates over the input frequency range of 4.5 to 9.2 GHz with better than -20 dBc suppressions of $1/3{\times}f_{in}\;and\;f_{in}$ tones, while dissipating 29 mA from 4.1 V supply.