• Journal of the Semiconductor & Display Technology
• /
• v.15 no.4
• /
• pp.22-26
• /
• 2016

In this paper, we measured the efficiency of the receiver for 5.8GHz Microwave Smartphone Charging. We have designed and fabricated 1W and 2W power amplifier, respectively. A 1W power amplifier used a TC3531 power device of TRANSCOM Inc. In addition, a 2W power amplifier using the two TC3531 devices was constructed with divider and combiner. We used the Wilkinson divider theory for divider and combiner. The voltage was measured using the 1W and 2W power amplifier and integrated receivers to the distance of 50cm.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.2
• /
• pp.283-288
• /
• 1996

This paper presents the development technology of standard shielded resistor divider for full lightning impulse voltage. The ability of large-capacity power apparatus to withstand lighting stroke is usually evaluated by means of full lightning impulse voltage. Lightning impulse voltage test has been essential to evaluate the insulation performance of electrical power apparatus. Recently international standard (IEC 60) on high voltage measurement techniques is being revised and requests a formal traceability of high voltage measurements. Therefore, general interest for this area has grown considerably during last years, and several international intercomparisons have already completed worldwide, i.e. Europe, Japan, America etc., In this viewpoint, we have also investigated the step response of the standard shielded resistor divider, which satisfies the IEC recommendation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.5
• /
• pp.396-401
• /
• 2000

In order to accurately measure the high voltage of 22.9[kV] power distribution lines we investigated the temperature dependence of measuring voltage on the number of stack layers in the voltage measurement system made from single and stack voltage divider capacitors (22, 44, 66 layers, respectively). Temperature coefficient of dielectric constant(TC$\varepsilon_{{\gamma}}$/)of voltage divider capacitors which were fabricated by BaTi $O_3$system ceramics showed the variations from -2.28% to +1.69% in the range of -25[$^{\circ}C$] ~50[$^{\circ}C$]) was decreased with increasing of stack number and the stack element of 66 layers showed the least error of $\pm$0.87%or of $\pm$0.87%.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.1
• /
• pp.198-203
• /
• 2000

In this paper, a numerical analysis is carried out to show the effect of friction farce on the dynamic characteristics of a flow divider valve. The continuity equations and the equation of motion fur spool are numerically solved. The viscous friction force acting on the spool is considered analyzing the Reynolds equation which governs the viscous flow in the clearance gap between the spool and sleeve. Dynamic characteristics are highly affected by the viscous friction farce whose magnitude is relatively small compare with other fluid forces. Therefore present theoretical formulation and numerical scheme can be used generally in designing and performance evaluation of all the hydraulic spool valve.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.6
• /
• pp.128-134
• /
• 2009

In this paper, we propose a new lumped Wilkinson power divider which is designed to have lower quality-factors in the impedance transformation. Therefore, it can provide wider bandwidth than the conventional one. Moreover, the proposed power divider consists of fewer number of elements so that the circuit size can be further reduced. Simulation results show that the proposed lumped power divider allows a 50% wider bandwidth in the return loss and isolation performance. The conventional and new Wilkinson power was designed and fabricated based on the derived equations at 2.0 GHz. In the measurement, the proposed divider achieved a good performance with an input return loss ($S_{11}$) of -23.0 dB, an isolation ($S_{23}$) of -29.0 dB and an insertion loss ($S_{21}$) of -3.12 dB at the design frequency with wider bandwidth than the conventional one.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.2
• /
• pp.107-114
• /
• 2009

In this paper, high efficiency amplifier configuration is proposed using the reconfigurable power divider. In order to enhance average efficiency of linear power amplifiers for wireless communication, it is required to increase efficiency in low output power region. The proposed power divider operates in two modes, high power mode and low power mode, according to output power. In each mode, it allows impedance matches and low loss, which is made possible by employing two $\lambda/4$ coupled lines and two switches. The fabricated power divider shows the return loss ($S_{11}$) and insertion loss ($S_{21}$) of -16.49 dB and -0.83 dB, respectively, in low power mode. In high power mode, the measured return loss ($S_{11}$) and insertion loss ($S_{31}$) are -16.28 dB and -0.73 dB, respectively. This result successfully demonstrates the reconfigurability of the proposed power divider.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.3
• /
• pp.33-42
• /
• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.7
• /
• pp.620-624
• /
• 2016

In this paper we designed a current mode logic frequency divider to transmit a baseband amplitude modulated signal. From simulation result, we studied input and output waveforms according to the variation of input bias voltage. For the purpose of the verification of the study, we designed a current mode logic frequency divider at 1,400 MHz. The designed frequency divider operates between 100 MHz and 3,000 MHz, for -33 dBm input power. The circuit draws $I_{total}=30mA$ from $V_{DD}=3V$ supply, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.5 was successfully downconverted to 700 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.12
• /
• pp.1712-1718
• /
• 2013

This paper proposes a compact dual-band 3-way power divider that helps lowering the weight of a transceiver for the L-band or multi-purpose satellite communication. Instead of the multi stages or tapering which ends up with loss accumulation and size-growth, the non-linear dispersive phases from the metamaterial CRLH(composite right and left-handed) properties are obtained by the accurate formulation and implemented by the short transmission line segments. Firstly, the CRLH dual-band two-way unequal power divider and equal power divider are separately designed. And then, the input of the two-way equal power divider is plugged in the output port of the unequal one, and the entire geometry is slightly adjusted for the desirable performance. The circuit analysis and full-wave simulation are used to predict the frequency responses and validated by the measurement of the prototype. Besides, the size-reduction effect is addressed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.10
• /
• pp.2341-2349
• /
• 2015

The commonly used Goldschmidt's floating-point divider algorithm performs two multiplications in one iteration. In this paper, a tentative error corrected K'th Goldschmidt's floating-point number divider algorithm which performs K times multiplications in one iteration is proposed. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation in single precision and double precision divider is derived from many reciprocal tables with varying sizes. In addition, an error correction algorithm, which consists of one multiplication and a decision, to get exact result in divider is proposed. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a divider unit. Also, it can be used to construct optimized approximate reciprocal tables.