• International Journal of Automotive Technology
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• v.6 no.2
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• pp.107-117
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• 2005

A distributed hardware-in-the-loop simulation (HILS) platform is developed for designing an automotive engine control system. The HILS equipment consists of a widely used PC and commercial-off-the-shelf (COTS) I/O boards instead of a powerful computing system and custom-made I/O boards. The distributed structure of the HILS system supplements the lack of computing power. These features make the HILS equipment more cost-effective and flexible. The HILS uses an automatic code generation extension, REAL-TIME WORKSHOP$^{ (RTW$^{) of MATLAB$^{ tool-chain and RT-LAB$^{, which enables distributed simulation as well as the detection and generation of digital event between simulation time steps. The mean value engine model, which is used in control design phase, is imported into this HILS. The engine model is supplemented with some I/O subsystems and I/O boards to interface actual input and output signals in real-time. The I/O subsystems are designed to imitate real sensor signals with high fidelity as well as to convert the raw data of the I/O boards to the appropriate forms for proper interfaces. A lot of attention is paid to the generation of a precise crank/ earn signal which has the problem of quantization in a conventional fixed time step simulation. The detection of injection! command signal which occurs between simulation time steps are also successfully compensated. In order to prove the feasibility of the proposed environment, a simple PI controller for an air-to-fuel ratio (AFR) control is used. The proposed HILS environment and I/O systems are shown to be an efficient tool to develop various control functions and to validate the software and hardware of the engine control system.

• Journal of the Korea Society for Simulation
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• v.18 no.2
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• pp.9-17
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• 2009

A face database has contained a large amount of facial information data since face recognition was widely used. With the increase of facial information data, the face recognition based on distributed processing method has been noticed as a major topic. In existing studies, there were lack of discussion about the transferring method for large data. So, we proposed a fuzzy logic-based bit compression rate selection method for distributed face recognition. The proposed method selects an effective bit compression rate by fuzzy inference based on face recognition rate, processing time for recognition, and transferred bit length. And, we compared the facial recognition rate and the recognition time of the proposed method to those of facial information data with no compression and fixed bit compression rates. Experimental results demonstrates that the proposed method can reduce processing time for face recognition with a reasonable recognition rate.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.140-142
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• 2010

영상 촬영기능을 갖는 휴대 단말의 보편화로 비디오 압축 방식의 새로운 접근 방법의 필요성이 대두되고 있다. 부호화기의 복잡도가 낮은 장점을 가진 분산 비디오 압축 기술은 이러한 필요성에 부합하는 기술로서 활발히 연구가 이루어지고 있는 분야이다. 본 논문은 분산 비디오 압축 기술에서 사용하고 있는 균일 양자화와 Deadzone을 알아보고, Deadzone의 크기를 조절하는 방법을 제안하여 율 왜곡 성능을 개선시키고, 제안 방법의 효과를 분석하였다.

• 한국HCI학회:학술대회논문집
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• 2006.02a
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• pp.931-936
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• 2006

This paper presents different issues of the real-time compression algorithms without compromising the video quality in the distributed environment. The theme of this research is to manage the critical processing stages (speed, information lost, redundancy, distortion) having better encoded ratio, without the fluctuation of quantization scale by using IP configuration. In this paper, different techniques such as distortion measure with searching method cover the block phenomenon with motion estimation process while passing technique and floating measurement is configured by discrete cosine transform (DCT) to reduce computational complexity which is implemented in this video codec. While delay of bits in encoded buffer side especially in real-time state is being controlled to produce the video with high quality and maintenance a low buffering delay. Our results show the performance accuracy gain with better achievement in all the above processes in an encouraging mode.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.289-292
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• 2002

This paper provides a frame-layer method for controlling bit rate of compressed video data in real time. Our approach is easy to operate and can store encoded video data in real time without deteriorating the quality of an image. To provide ameliorated and consistent visual quality, a new concept named SOP (Set Of Pictures) and a new quantization parameter variation control algorithm based on a second-order rate-distortion model 〔2〕 are introduced. The total bit-budget is allocated efficiently to cope with unpredictable recording time by using the proposed algorithm and it is distributed to each frame. In the end, we show improved and consistent video quality with experimental results obtained from C-model of a MPEG-4 (simple-profile) encoder.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Journal of IKEEE
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• v.24 no.1
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• pp.40-45
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• 2020

In this paper, we consider an efficient design of quantizers at sensor nodes for sequence-based localization (SBL) systems which recently show a competitive performance for in-door positioning, Since SBL systems locate targets by partitioning the sensor field into subregions, each with an unique sequence number, we use the distance samples between sensors and the sequences for quantizer design in order to propose a low weight design process. Furthermore, we present a new cost function devised to assign the number of samples and the number of unique sequences uniformly into each of quantization partitions and design quantizers by searching the quantization partitions and codewords that minimize the cost function. We finally conduct experiments to demonstrate that the proposed algorithm offers an outstanding localization performance over typical designs while maintaining a substantial reduction of design complexity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.128-138
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• 2010

In this paper, we propose a new bit assignment scheme for Wyner-Ziv video coding. Distributed video coding (DVC) is a new video coding paradigm which enables greatly low complexity encoding because it does not have any motion prediction module at encoder. Therefore, it is very well suited for many applications such as video communication, video surveillance, extremely low power consumption video coding, and other portable applications. Theoretically, the Wyner-Ziv video coding is proved to achieve the same rate-distortion (RD) performance comparable to that of the joint video coding. However, its RD performance has much gap compared to MC-DCT-based video coding such as H.264/AVC. Moreover, Transform Domain Wyner-Ziv (TDWZ) video coding which is a kind of DVC with transform module has difficulty of exact bit assignment because the entire image is treated as a same message. In this paper, we propose a feasible bit assignment algorithm using adaptive quantization matrix selection for the TDWZ video coding. The proposed method can calculate suitable bit amount for each region using the local characteristics of image. Simulation results show that the proposed method can enhance coding performance.