• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.44-51
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• 1999

This paper presents a massively parallel computational model for the efficient integration of speech and natural language understanding. The phoneme model is based on continuous Hidden Markov Model with context dependent phonemes, and the language model is based on a knowledge base approach. To construct the knowledge base, we adopt a hierarchically-structured semantic network and a memory-based parsing technique that employs parallel marker-passing as an inference mechanism. Our parallel speech recognition algorithm is implemented in a multi-Transputer system using distributed-memory MIMD multiprocessors. Experimental results show that the parallel speech recognition system performs better in recognition accuracy than a word network-based speech recognition system. The recognition accuracy is further improved by applying code-phoneme statistics. Besides, speedup experiments demonstrate the possibility of constructing a realtime parallel speech recognition system.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.04a
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• pp.389-395
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• 2004

We consider the interface between the parallel distributed memory multifrontal solver and the finite element method. We give in detail the requirement and the data structure of parallel FEM interface which includes the element data and the node array. The full procedures of solving a large scale structural problem are assumed to have pre-post processors, of which algorithm is not considered in this paper. The main advantage of implementing the parallel FEM interface is shown up in the case that we use a distributed memory system with a large number of processors to solve a very large scale problem. The memory efficiency and the performance effect are examined by analyzing some examples on the Pegasus cluster system.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.1-8
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• 2019

Modern computers provide tremendous computing capability and a large memory system. Hybrid memories consist of next generation memory devices and are adopted in high performance systems. However, the increased complexity of the microprocessor makes it difficult to operate the system effectively. In this paper, we propose a simple data migration method called Bandwidth-aware Data Migration (BDM) to efficiently use memory systems for high performance processors with hybrid memory. BDM monitors the status of applications running on the system using hardware performance monitoring tools and migrates the appropriate pages of selected applications to High Bandwidth Memory (HBM). BDM selects applications whose bandwidth usages are high and also evenly distributed among the threads. Experimental results show that BDM improves execution time by an average of 20% over baseline execution.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Journal of applied mathematics & informatics
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• v.29 no.1_2
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• pp.211-225
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• 2011

In this paper, a class of bi-directional associative memory (BAM) fuzzy cellular neural networks with distributed delays and impulses is formulated and investigated. By employing an integro-differential inequality with impulsive initial conditions and the topological degree theory, some sufficient conditions ensuring the existence and global exponential stability of equilibrium point for impulsive BAM fuzzy cellular neural networks with distributed delays are obtained. In particular, the estimate of the exponential convergence rate is also provided, which depends on the delay kernel functions and system parameters. It is believed that these results are significant and useful for the design and applications of BAM fuzzy cellular neural networks. An example is given to show the effectiveness of the results obtained here.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1867-1879
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• 1997

DREAM-S is a distributed main-memory database system for the real-time processing of shared operational datra in ATM switching systems. DREAM-S has a client-server architecture in which only the server has the diskstorage, and provides the T-Tree index structure for efficient accesses to the data. We propose a recovery technique for the T-Tree index structre in DREAM-S. Although main-memory database system offer efficient access performance, the database int he main-memory may be broken when system failure such as database transaction failure or power failure occurs. Therfore, a recovery technique that recovers the database (including index structures) is essential for fault tolerant ATM switching systems. Proposed recovery technique relieves the bottleneck of the server processors disk operations by maintaining the T-Tree index structure only in the main-memory. In addition, fast recovery is guaranteed even in large number of client systems since the T-Tree index structure(s) in each system can be recovered cncurrently.

• KIISE Transactions on Computing Practices
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• v.22 no.1
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• pp.44-49
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• 2016

Recently, data has been growing dramatically along with the growth of social media and digital devices. A distributed memory processing system has been used to efficiently process large amounts of data. However, if a load is concentrated in a certain node in distributed environments, a node performance significantly degrades. In this paper, we propose a load balancing scheme to distribute load in a distributed memory environment. The proposed scheme replicates hot data to multiple nodes for managing a node's load and migrates the data by considering the load of the nodes when nodes are added or removed. The client reduces the number of accesses to the central server by directly accessing the data node through the metadata information of the hot data. In order to show the superiority of the proposed scheme, we compare it with the existing load balancing scheme through performance evaluation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2230-2234
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• 2003

This paper proposes a distributed simulator for general control system in CEMTool. Systems can be described by SIMTool likes the simulink in Matlab. For distributed simulation, we can seperate any system into several parallel subsystems in SIMTool. The number of parallel subsystem can be determined by the system's property. After seperation, parallel simulator will do initialization, one-step-ahead simulation, block-distribution and ordering and so on. Finally, simulator will create independent C codes and executive files for each subsystem. The whole system is fulfilled by several PCs, and each PC executes one subsystem. There are communications among these subsystem using reflective memory or ethernet. We have made several experiments, and the 5-stand cold rolling mill control system is our main target. The result of parallel simulation has shown effective speedup in comparison with one pc simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.127-134
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• 2019

With the advancement of IT technology, the amount of data generated has been growing exponentially every year. As an alternative to this, research on distributed systems and in-memory based big data processing schemes has been actively underway. The processing power of traditional big data processing schemes enables big data to be processed as fast as the number of nodes and memory capacity increases. However, the increase in the number of nodes inevitably raises the frequency of failures in a big data infrastructure environment, and infrastructure management points and infrastructure operating costs also increase accordingly. In addition, the increase in memory capacity raises infrastructure costs for a node configuration. Therefore, this paper proposes an in-memory-based hybrid big data processing scheme for improve the big data processing rate. The proposed scheme reduces the number of nodes compared to traditional big data processing schemes based on distributed systems by adding a combiner step to a distributed system processing scheme and applying an in-memory based processing technology at that step. It decreases the big data processing time by approximately 22%. In the future, realistic performance evaluation in a big data infrastructure environment consisting of more nodes will be required for practical verification of the proposed scheme.