• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Korean Society for Heat Treatment
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• v.27 no.5
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• pp.230-234
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• 2014

IGZO/Ag bi-layered films were deposited on glass substrate at room temperature with radio frequency and direct current magnetron sputtering, respectively to consider the effect of Ag buffer layer on the electrical, optical and structural properties. For all deposition, while the thickness of Ag buffer layer was varied as 10, 15, and 20 nm, The thickness of IGZO films were kept at 100 nm, In a comparison of figure of merit, IGZO films with 15 nm thick Ag buffer layer show the higher figure of merit ($1.1{\times}10^{-2}{\Omega}^{-1}$) than that of the IGZO single layer films ($3.7{\times}10^{-4}{\Omega}^{-1}$). From the observed results, it is supposed that the IGZO 100 nm/Ag 15 nm bi-layered films may be an alternative candidate for transparent electrode in a transparent thin film transistor device.

• Journal of the Korean institute of surface engineering
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• v.55 no.2
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• pp.91-95
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• 2022

ZnO single layer (60 nm thick) and ZnO with Ag interlayer (ZnO/Ag/ZnO; ZAZ) films were deposited on the glass substrates by using radio frequency (RF) and direct current (DC) magnetron sputter to evaluate the effectiveness of Ag interlayer on the optical visible transmittance and the conductivity of the films. In the ZAZ films, the thickness of ZnO layers was kept at 30 nm, while the Ag thickness was varied as 5, 10, 15 and 20 nm. In X-ray diffraction (XRD) analysis, ZnO films show the (002) diffraction peak and ZAZ films also show the weak ZnO (002) peak and Ag (111) diffraction peak. As a thickness of Ag interlayer increased to 20 nm, the grain size of the Ag films enlarged to 11.42 nm and the optical band gap also increased from 4.15 to 4.22 eV with carrier concentration increasing from 4.9 to 10.5×10²¹ cm^-3. In figure of merit measurements, the ZAZ films with a 10 nm thick Ag interlayer showed the higher figure of merit of 4.0×10^-3 Ω^-1 than the ZnO single layer and another ZAZ films. From the experimental result, it is assumed that the Ag interlayer enhanced effectively the opto-electrical performance of the ZAZ films.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.93-93
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• 2017

고전력 펄스 전원공급장치를 이용한 마그네트론 스퍼터링(high-power impulse magnetron sputtering; HiPIMS)과 직류(direct current; DC) 전원공급장치를 이용한 마그네트론 스퍼터링(DC 스퍼터링)을 이용하여 제조한 티타늄 질화물(titanium nitride; TiN) 박막의 특성을 비교하였다. HiPIMS와 DC 스퍼터링 공정 중에 빗각증착을 적용하여 TiN 박막의 미세구조와 기계적 특성의 변화를 확인하였다. TiN 박막을 코팅하기 위한 기판으로 스테인리스 강판(SUS304)과 초경(cemented carbide; WC-10wt.%Co)을 사용하였다. 기판은 알코올과 아세톤으로 초음파 처리를 실시하여 기판 표면의 불순물을 제거하였다. 기판 청정 후 진공용기 내부의 기판홀더에 기판을 장착하고 $2.0{\times}10^{-5}torr$의 기본 압력까지 진공배기를 실시하였다. 진공 용기의 압력이 기본 압력에 도달하면 아르곤(Ar) 가스를 진공용기 내부로 ${\sim}10^{-2}torr$의 압력으로 주입하고 기판홀더에 라디오 주파수(radio frequency; rf) 전원공급장치를 이용하여 - 800 V의 전압을 인가하여 글로우 방전을 발생시켜 30 분간 기판 표면의 산화막을 제거하는 기판청정을 실시하였다. 기판청정이 완료되면 기본 압력까지 진공배기를 실시하고 Ar과 질소($N_2$)의 혼합 가스를 진공용기 내부로 ${\sim}10^{-3}torr$의 압력으로 주입하여 HiPIMS와 DC 스퍼터링으로 TiN 박막 제조를 실시하였다. 빗각의 크기는 $45^{\circ}$와 $-45^{\circ}$이었다. 제조된 TiN 박막은 주사전자 현미경, 비커스 경도 측정기 그리고 X-선 회절 분석기를 이용하여 특성을 분석하였다. HiPIMS로 제조한 TiN 박막은 기판 전압을 인가하지 않아도 색상이 노란색을 보이지만, DC 스퍼터링으로 제조한 TiN 박막은 기판 전압을 인가하지 않으면 노란색을 보이지 않고 어두운 갈색에 가까운 색을 보였다. TiN 박막의 경도는 HiPIMS로 제조한 TiN 박막이 DC 스퍼터링으로 제조한 TiN 박막보다 높았다. 이러한 TiN 박막의 특성 차이는 DC 스퍼터링과 비교하여 높은 HiPIMS의 이온화율에 의한 결과로 판단된다. 빗각을 적용한 TiN 박막은 미세구조 변화를 보였으며 이러한 미세구조 변화는 TiN 박막의 특성에 영향을 미치는 것을 확인하였다.

• Corrosion Science and Technology
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• v.18 no.5
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• pp.206-211
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• 2019

Silicon carbide (SiC) thin films become superhard when they have microstructures of nanocolumnar crystalline grains (NCCG) with an intergranular amorphous SiC matrix. We investigated the role of ion bombardment and deposition temperature in forming the NCCG in SiC thin films. A direct-current (DC) unbalanced magnetron sputtering method was used with pure Ar as sputtering gas to deposit the SiC thin films at fixed target power of 200 W and chamber pressure of 0.4 Pa. The Ar ion bombardment of the deposited films was conducted by applying a negative DC bias voltage 0-100 V to the substrate during deposition. The deposition temperature was varied between room temperature and $450^{\circ}C$. Above a critical bias voltage of -80 V, the NCCG formed, whereas, below it, the SiC films were amorphous. Additionally, a minimum thermal energy (corresponding to a deposition temperature of $450^{\circ}C$ in this study) was required for the NCCG formation. Transmission electron microscopy, Raman spectroscopy, and glancing angle X-ray diffraction analysis (GAXRD) were conducted to probe the samples' structural characteristics. Of those methods, Raman spectroscopy was a particularly efficient non-destructive tool to analyze the formation of the SiC NCCG in the film, whereas GAXRD was insufficiently sensitive.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.139-139
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• 2010

금속 실리사이드 나노입자는 열적 및 화학적 안정성이 뛰어나고, 절연막내에 일함수 차이에 따라 깊은 양자 우물구조가 형성되어 비휘발성 메모리 소자를 제작할 수 있다. 그러나 단일 $SiO_2$ 절연막을 사용하였을 경우 저장된 전하의 정보 저장능력 및 쓰기/지우기 시간을 향상시키는 데 물리적 두께에 따른 제한이 따른다. 본 연구에서는 터널장벽 엔지니어링을 통하여 물리적인 두께는 단일 $SiO_2$ 보다는 두꺼우나 쓰기/지우기 동작을 위하여 인가되는 전기장에 의하여 상대적으로 전자가 느끼는 상대적인 터널 절연막 두께를 감소시키는 방법으로 동작속도를 향상 시킨 $SiO_2/Si_3N_4/SiO_2$ 및 $Si_3N_4/SiO_2/Si_3N_4$ 터널 절연막을 사용한 금속 실리사이드 나노입자 비휘발성 메모리를 제조하였다. 제조방법은 우선 p-type 실리콘 웨이퍼 위에 100 nm 두께로 증착된 Poly-Si 층을 형성 한 이후 소스와 드레인 영역을 리소그래피 방법으로 형성시켜 트랜지스터의 채널을 형성한 이후 그 상부에 $SiO_2/Si_3N_4/SiO_2$ (2 nm/ 2 nm/ 3 nm) 및 $Si_3N_4/SiO_2/Si_3N_4$ (2 nm/ 3 nm/ 3 nm)를 화학적 증기 증착(chemical vapor deposition)방법으로 형성 시킨 이후, direct current magnetron sputtering 방법을 이용하여 2~5 nm 두께의 $WSi_2$ 및 $TiSi_2$ 박막을 증착하였으며, 나노입자 형성을 위하여 rapid thermal annealing(RTA) system을 이용하여 $800{\sim}1000^{\circ}C$에서 질소($N_2$) 분위기로 1~5분 동안 열처리를 하였다. 이후 radio frequency magnetron sputtering을 이용하여 $SiO_2$ control oxide layer를 30 nm로 증착한 후, RTA system을 이용하여 $900^{\circ}C$에서 30초 동안 $N_2$ 분위기에서 후 열처리를 하였다. 마지막으로 thermal evaporator system을 이용하여 Al 전극을 200 nm 증착한 이후 리소그래피와 식각 공정을 통하여 채널 폭/길이 $2{\sim}5{\mu}m$인 비휘발성 메모리 소자를 제작하였다. 제작된 비휘발성 메모리 소자는 HP 4156A semiconductor parameter analyzer와 Agilent 81101A pulse generator를 이용하여 전기적 특성을 확인 하였으며, 측정 온도를 $25^{\circ}C$, $85^{\circ}C$, $125^{\circ}C$로 변화시켜가며 제작된 비휘발성 메모리 소자의 열적 안정성에 관하여 연구하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.257.1-257.1
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• 2014

We investigated characteristics of ITO/Ag-Pd-Cu (APC)/ITO multilayer electrodes prepared by direct current magnetron sputtering for use as an anode in organic solar cells (OSCs). To optimize electrical properties of ITO/APC/ITO multilayer, we fabricated the ITO/APC/ITO multilayer at a fixed ITO thickness of 30 nm as a function of APC thickness. Compare to the surface of Ag layer on ITO, the APC had a smooth surface morphology. At optimized APC thickness of 12 nm, the ITO/APC/ITO multilayer exhibited a sheet resistance of $6{\Omega}/square$ and optical transmittance of 84.15% at a wavelength of 550 nm which is comparable to conventional ITO/Ag/ITO multilayer. However, the APC-based ITO multilayer showed a higher average transmittance in a visible region than the Ag-based ITO multilayer. The higher average transmittance of ITO/APC/ITO multilayer indicated the multilayer is suitable anode for organic solar cells with P3HT:PCBM active layer. OSCs fabricated on the optimized ITO/ACP/ITO multilayer exhibited a better performance with a fill factor of 64.815%, a short circuit current of $8.107mA/cm^2$, an open circuit voltage of 0.59 V, and power conversion efficiency (3.101%) than OSC with ITO/Ag/ITO multilayer (2.8%).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.751-757
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• 2000

The r.f. power effect for Pt doping is investigated on structural and electrochemical properties of amorphous vanadium oxide(V$_2$O$_{5}$) film, grown by direct current (d.c.) magnetron sputtering. Room temperature charge-discharge measurements based on a half-cell with a constant current clearly indicated that the Pt doping could improve the cyclibility of V$_2$O$_{5}$ cathode film. Using glancing angle x-ray diffraction(GXRD) and high-resolution transmission electron microscopy (HRTEM) analysis, we found that the Pt doping with 10W r.f. power induces more random amorphous structure than undoped V$_2$O$_{5}$ film. As the r.f. power of Pt target increases. large amount of Pt atoms incorporates into the amorphous V$_2$O$_{5}$ film and makes $\alpha$-PtO$_2$microcrystalline phase in the amorphous V$_2$O$_{5}$ matrix. These results suggest that the semiconducting $\alpha$-PtO$_2$ microcrystalline phase in amorphous matrix lead to a drastically faded cyclibility of 50W Pt doped V$_2$O$_{5}$ cathode film. Possible explanations are given to describe the Pt doping effect on cyclibillity of the amorphous V$_2$O$_{5}$ cathode film battery. film battery.

• Journal of the Korean Magnetics Society
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• v.2 no.3
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• pp.277-281
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• 1992

We have designed, fabricated and tested an integrated planar DC SQUID which incorporates input coil and mofulation coil in thin film structure. The SQUID uses Nb /Al-oxide /Nb Josephson junctions and Pd shunt resistors, and the SQUID loop incorporates two rings connected in series forming figure '8' structure and has the advantage of a negligibly small circulating current for the spatially homogeneous noise fields. The devices were fabricated using photolithographic technique, RF magnetron sputtering, anodic oxidation for insulation and lift-off process. The preliminary test of the fabricated SQUID at 4.2 K showed that the flux-voltage characteristics were smooth enough to adopt standard readout system, and the voltage noise was too small to be measured by direct method and so the white noise was thought to be less than $10^{-4}\;{\phi}_o/\;\sqrt{H_z}$.