• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.251-257
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• 2015

This work presents modelling and simulation of a readout integrated circuit (ROIC) design considering pair-wise serial configuration along with thermal modeling of an uncooled microbolometer array. A fully differential approach is used at the input stage in order to reduce fixed pattern noise due to the process variation and self-heating-related issues. Each pair of microbolometers is pulse-biased such that they both fall under the same self-heating point along the self-heating trend line. A ${\pm}10%$ process variation is considered. The proposed design is simulated with a reference input image consisting of an array of $127{\times}92$ pixels. This configuration uses only one unity gain differential amplifier along with a single 14-bit analog-to-digital converter in order to minimize the dynamic range requirement of the ROIC.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1517-1518
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• 2006

This paper describes the design and fabrication of a partial discharge(PD) analyzer to evaluate insulation performance for low-voltage electrical and electronic devices. The analyzer consists of an adjustable AC power supply, a coupling network, an amplifier, a shielding encloser, a sample-hold (S/H) circuit and a data acquisition (DAQ) board. The analyzer holds the height of PD pulse for $10{\mu}s$ by the S/H circuit, and this makes possible to measure PD pulses having fast rise and short duration by a low speed analog-to-digital (A/D) converter. The data are transmitted to the personal computer through the DAQ board, and the designed analysis program calculate apparent charges, discharge inception and extinction voltages.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.30-36
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• 2012

A new BIST(Built-In Self-Test) scheme to test ADC(Analog-to-Digital Converter) with a transition detector is proposed. The proposed BIST is able to replaces histogram method, the most popular approach in static testing of ADC. With a ramp signal as an input test stimulus, the proposed BIST calculates ADC's static parameters such as offset, gain, INL(Integral Non-Linearity) and DNL(Differential Non-Linearity). The three detectors in the proposed BIST can deal with a transient zone problem, a phenomenon due to random noise in real test environments and are cost efficient at various acceptable ranges determined as a test spec. The simulation results validate that our method performs accurate static test and show the reduction of the hardware overhead.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.365-367
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• 2013

본 논문에서는 $0.18{\mu}m$ CMOS 공정 기술을 이용하여 12-bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 진행하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 5.5mW였고, 입력 신호의 주파수가 100kHz일 때, SNDR은 70.03dB, 유효 비트수는 11.34bit의 결과를 보였다. 설계된 변환기는 $0.8mm{\times}0.7mm$ 크기로 레이아웃 되었다.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.443-445
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• 1990

In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.04a
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• pp.449-452
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• 2004

To obtain the ultra-sharp tungsten tip, an analog to digital converter circuit aided by a personal computer has been setup. At the moment the lower part of the needle drops off during the etching process, a maximum current change across the reference resistor is detected by the PC interface card and the applied voltage is then cut off within a few milliseconds. Out experiment has been able to fabricate an ultra-sharp tungsten tip ~200 $\AA$ radius with a higher reproduction rate and reliability than the conventional method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.638-641
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• 2000

The conventional motor in a crane has a tan generator to feed back the number of turns. The tan generator is contacted to a motor shaft through the coupling. Don has been often generated because the coupling has worn out while the motor is turning. In this paper, we design the speed-measurement device of motor in a un. The device is composed of PIC16F84 controller, photo-sensor, and analog-to digital converter. The photo sensor measures the turn of a motor without contact so the device decreases the probability of errors. And The device can acknowledge the turn direction of the motor with a gin81e senor and two color reflectors.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.69-71
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• 2005

This paper presents a wavelet-based neural network technology for the detection and classification of the short durations type of power quality disturbances. Transients happen during very short durations to the nano- and microsecond. Thus, a method for detecting and classifying transient signals at the same time and in an automatic combines the properties of the wavelet transform and the advantages of neural networks. Especially, the additional feature extraction to improve the recognition rate is considered. The configuration of the hardware of TMS320C6711 DSP based with 16 channel 20Mhz sampling rate A/D(Analog to Digital) converter and some case studies are described.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.437-440
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• 1992

We design a multi-element photo-detector to measure the size of particles using the diffracted light energy distribution. The light energy that is scattered by particles in the collimated laser beam is collected by the Fourier transform lens and directed to the multi-semicircular concentric annular detecters. The scattered profile measured by the photodetector is sampled by a 32 channel analog-to-digital converter. A nonnegative least squares analysis translates the light energy distribution into the corresponding unique particle size distribution.