• ETRI Journal
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• 제26권1호
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• pp.53-56
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• 2004

In this letter, we propose a novel design scheme for an optimal non-uniform planar array geometry in view of maximum side-lobe reduction. This is implemented by a thinned array using a genetic algorithm. We show that the proposed method can maintain a low side-lobe level without pattern distortion during beam steering.

• ETRI Journal
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• 제28권1호
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• pp.9-16
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• 2006

In this paper, we analyzed and measured the electrical crosstalk characteristics of a 1.25 Gbps triplexer module for Ethernet passive optical networks to realize fiber-tothe-home services. Electrical crosstalk characteristic of the 1.25 Gbps optical triplexer module on a resistive silicon substrate should be more serious than on a dielectric substrate. Consequently, using the finite element method, we analyze the electrical crosstalk phenomena and propose a silicon substrate structure with a dummy ground line that is the simplest low-crosstalk layout configuration in the 1.25 Gbps optical triplexer module. The triplexer module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and an analog photodetector as a cable television signal receiver. According to IEEE 802.3ah and ITU-T G.983.3, the digital receiver and analog receiver sensitivities have to meet -24 dBm at $BER=10^{-12}$ and -7.7 dBm at 44 dB SNR. The electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the dummy line with $100\;{\mu}m$ space from the signal lines and 4 mm separations among the devices satisfies the electrical crosstalk level compared to a simple structure. This proposed structure can be easily implemented with design convenience and greatly reduce the silicon substrate size by about 50 %.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.718-727
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• 2014

In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2005년도 춘계학술대회 논문집
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• pp.34-39
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• 2005

The progress of silicon technology enables to implement a highly complex digital system on a given chip area. However, even the modern design environment is not so efficient to catch up with the progress of process technology. Design reuse is a promising approach to designing such a complex system in an efficient way. However, the rigidness and inflexibility of a model has been an obstacle to design reuse. This paper proposes a high-level model management methodology by introducing attributed AND-OR graph(AOG), a (formal semantics for representing the possible structure of a model. Using the formalism enables a designer to extract, extend and reuse the pre-modeled and pre-verified design. A complete process of constructing a cache operational model, extending the model and extracting executable models is exemplified to show effectiveness of the proposed framework.

• 한국콘텐츠학회논문지
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• 제10권5호
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• pp.124-134
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• 2010

본 연구는 디지털콘텐츠디자인을 처음 접하는 시각정보미디어 전공 학생들이 보다 손쉽고 효과적으로 디지털콘텐츠디자인 개발에 접근할 수 있도록 하는 방법이 무엇인지를 찾기 위해 진행되었다. 연구목표는 디지털콘텐츠디자인 개발 과정의 일환으로서 동일 주제의 아날로그콘텐츠 제작을 선행적으로 수행하는 것의 유의성을 파악하는 것이다. 연구를 통해 얻어진 결과는 첫째, 정보구조화 단계에서 전체적인 정보를 체계화시키는 과정의 심리적 부담을 덜어주는데 도움을 준다. 둘째, 정보디자인 단계에서 정보디자인의 대상과 형식을 효과적으로 파악하는데 유용하다. 셋째, 아날로그콘텐츠와 디지털콘텐츠의 차이에 대한 이해를 통해 디지털콘텐츠디자인의 특성을 명확하게 이해하는데 도움을 준다.

• 한국게임학회 논문지
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• 제5권3호
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• pp.17-24
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• 2005

디지털미디어의 상호작용성의 특징은 전통적인 스토리텔링을 변화시켜 디지털 스토리텔링이라는 새로운 개념으로 자리 잡고 있다. 게임 스토리텔링은 영화나 애니메이션의 전개방식과는 달리 개방형스토리 전개방식(open ended design)을 택하고 있으며, 플레이어 캐릭터(player character)의 선택(player's decision)에 따라 무한개의 스토리를 만들어 낼 수 있다. 가장 스토리 중심적인 RPG장르에서 캐릭터를 중심으로 한게임 스토리텔링 구조를 제안하고, 다양한 스토리 밸류(Story value)를 가지고 디자인되어 있는 캐릭터들이 게임 스토리텔링 구조(Game Storytelling Structure) 속에서 플레이어의 흥미와 몰입을 가져오는 배경이야기(Background Story), 판타지적인 게임월드(Game World)과 그 속에서 발생하는 사건(Event)들과 어떻게 상호작용하는지 사례를 통해 분석하였다. 본 연구는 예측 가능한 게임 메카닉(game mechanics)설계와 특별한 목표를 가지고 있는 게임인 경우 게임 플레이를 통제할 수 있는 수단이 되는 필수적인 작업이다.

• ETRI Journal
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• 제26권6호
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1987년도 춘계학술발표회 논문집
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• pp.219-222
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• 1987

A Semi-cusion VLSI Digital Filter Design for TDM/FDM tran-smultiplexer is decribed. Using the polyphase network approach a filter bank composed of only all-pasdigital filter sections was designed. The use of all-pass filters as basic building blocks is shown to provide a Transmultiplexer structure that has low computational requirements low quanization noise and hign modularity. A design of 1st order 2nd All pass filter is done using COMS 2um double metal.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• 한국디자인학회:학술대회논문집
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• 한국디자인학회 2003년도 봄 학술발표대회논문집
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• pp.268-269
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• 2003