• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.5
• /
• pp.55-62
• /
• 2011

In this paper, a temporal color and luminance variation suppression algorithm for a digital video sequence is proposed by considering time-varying light source. When a video sequence is sampled with the periodically emitting illuminant and with a short exposure time, the color rolling phenomenon occurs, where the color and the luminance of the image periodically change from field to field. In conventional signal processing techniques, the luminance variation remaining in the resultant video sequence degrades the constancy of the image sequence. In the proposed method, we obtain video sequences with constant luminance and color by compensating for the inter-field luminance variation. Based on a motion detection technique, the amount of the luminance variation for each channel is estimated on the background of the sequence without the effects of moving objects. The experimental results clearly show that our strategy efficiently estimated the illuminant change without being affected by moving objects, and the variations were efficiently reduced.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.9
• /
• pp.57-66
• /
• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• Journal of IKEEE
• /
• v.11 no.1 s.20
• /
• pp.30-37
• /
• 2007

This paper proposes a detection method of position of OFF-switch. Each switch has the parallel path with a serial combination of passive element, its parallel path has each different frequency characteristics. Frequency characteristic of ON-switch reveals a flat spectrum irrelevant to frequency characteristic of passive element connected in parallel to its each terminal and frequency characteristic of OFF-switch reveals the same characteristic as one of passive element connected in parallel. Detection of position of OFF-switch is done by measuring the similarity of each spectrum corresponding to frequency characteristic of passive element connected in parallel to OFF-switch. The measure of their similarity is to calculate Euclidean distance between their test spectrum and reference spectrum. The spectrum with the smallest distance among reference spectrum is recognized as the spectrum of OFF-switch. The real time digital signal processing system is implemented to detect the position of OFF-switch by using spectrum matching.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.10
• /
• pp.1433-1443
• /
• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.5
• /
• pp.209-213
• /
• 2010

This paper is a study of Car safety network system using sensed data from varied sensors. This hardware will work with various sensors and communication protocols. There are many sensors. Then, I selected 3 sensors for test, which were sonic sensor for distance checking, tilt sensor for rollover and impact sensor for car accident and theft. Also, there are many interfaces for sensor. Therefore I designed hardware to support various sensor interfaces. For instance ADC(Analog to Digital converter), I2C, RS232, RS485, CAN. In this case, sonic sensor have I2C interface, tilt sensor have RS485 interface and Impact sensor have analog interface. In this research, I can gather sensing data from 3 sensors (mentioned above), and sending control signal to other processor with RS232, RS485, CAN communication. So, we can use easily this hardware for many cases of systems, which need sensors.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.4
• /
• pp.53-58
• /
• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.8
• /
• pp.1631-1641
• /
• 2012

A TDMA system in satellite communication has been utilized. Especially DVB-S2 was standardized and now operated in satellite broadcasting system. In this paper, we propose a TDMA frame structure appropriate for special purpose which has the good reliablilty in a poor RF environment even if frequency efficiency is decreased. TDMA frame duration is 12 seconds which is long duration in comparison with general TDMA system with several ms. Designing the frame structure, time and frequency shift in single frame duration are considered. Simulation results show that the proposed frame structure and synchronization method has robust synchronization performance when the terminal is even in low SNR as well as 25 kHz frequency offsets.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.283-288
• /
• 2018

In this paper, it is required that the next generation wireless transmission system can support a large number of users without distortion of transmission signal with high data rate in various different propagation environment while using limited resources as efficiently as possible, and therefore an efficient transmission system is continuously required. Because of the large amount of data to be handled in a limited frequency band, a very complex digital modulation scheme is adopted. the linearity of the power amplifier determines the linearity of the entire communication system, and thus a linear amplifier is required. In cognitive radion systems, there is a power control issue in the relationship between primary and secondary users. This problem is solved by simulating the communication system so as to select the cognitive radio power while power control while overcoming linearity by using feed-forward PA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.6
• /
• pp.1375-1381
• /
• 2010

LED(Light Emitting Diode) is an emitting device which energy is same to the bandgap energy of p-type and n-type semiconductor junction. Recently high brightness LED is used in fish-luring light and traffic signal light alternative of normal light bulb, and widely used in the area of display pannel. Moreover nowadays LED has been used as a back light of LCD display. Recently, visible light communication(VLC) using LED, that allow two-way serial data communication between LEDs over a distance of sveral centimeters or meters, has been widely studied in the area of digital information transmission along with illumination and display. In this paper, we present LED communication system and their applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.11
• /
• pp.2479-2485
• /
• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.