• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• The Journal of the Acoustical Society of Korea
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• v.16 no.2
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• pp.80-88
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• 1997

In this paper, the implementation of audio/data processor using ETRI DSP to support analog mode in digital/analog dual mode mobile phone is presented. Audio/data processor performs the wideband data processing, audio signal processing, demodulation function, and data rate conversion when it is operated in analog mode. These functions are programmed in assembly language, and then loaded to ETRI DSP together with vocoder program for the digital mode operation. This is a very efficient implementation of the dual mode cellular phone ASIC since the vocoder for the digital mode and audio/data processor for the analog mode are programmed together in the same hardware.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• The Journal of the Acoustical Society of Korea
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• v.24 no.4
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• pp.186-193
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• 2005

The Terrestrial Digital Multimedia Broadcasting (T-DMB) system supplies high quality audio comparable with VCD in 7 inch display and high quality audio comparable CD at the mobile reception environment T-DMB will launch commercial service at the middle of 2005. However the bandwidth for audio data and the number of channels are restricted to 128 kbps and 2 respectively in the current T-DMB standard because of the limitation of available bandwidth for multimedia data. This Paper Proposes a novel media processor structure for providing multi-channel audio contents oyer T-DMB system allowing backward compatibility with the legacy T-DMB receiver. Furthermore. we also Propose an adaptive receiver structure to supply optimal audio contents on various speaker configuration in T-DMB receiver. To provide multi-channel audio contents allowing backward comaptilbity with the legacy T-DMB receiver, the additional data for multi-channel audio are defined as a dependent stream of main audio stream. The OD strucure for control an additional multi-channel audio elementary stream is proposed without changing the BIFS of the legacy T-DMB system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.12-18
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• 2008

This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1011-1012
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• 2006

In this paper, implementation process of standard platform for T-DMB Receiver in low-cost and small-size are following: First, implement SoC for 32 bit RISC CPU and 16 bit DSP, Hardware H.264 CODEC, Post Processor or Video Display, Audio Processor, I/O Device. Second, implement Real Time OS for flexible application. Third, propose simple architecture for interface with peripheral devices using one-chip processor.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.477-481
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• 2004

High Quality CD, OAT audio requires that large amount of data. Currently, multi channel preference has been rapidly propagated among latest users. The MPEG(Moving Picture Expert Group) is provides data compression technology of sound and image system. The MPEG standard provides multi channel and 5.1 sounds, using the same audio algorithm as MPEG-l. And MPEG-2 audio is forward and backward compatible. The MDCT (Modified Discrete Cosine Transform) is a linear orthogonal lapped transform based on the idea of TDAC(Time Domain Aliasing Cancellation). In this paper, we proposed the micro-program type vector processor architecture a benefit in MDCT/IMDCT of MPEG-II AAC. And it's reduced operating coefficient by overlapped area to bind. To compare original algorithm with optimized algorithm that cosine coefficient reduced $0.5\%$multiply operating $0.098\%$ and add operating 80.58\%$. Algorithm test is used C-language then we designed hardware architecture of micro-programmed method that applied to optimized algorithm. This processor is 20MHz operation 5V.