• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.1 no.2
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• pp.27-31
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• 2000

Thermal imaging system is implemented for the measurement and the analysis of the thermal distribution of the target objects. The main Part of the system is thermal camera in which a focal plane array typed sensor is introduced The sensor detects mid-range infrared spectrum or target objects and then it output generic video signal which should be processed to form a thermal image frame. A digital signal processor(DSP) in the system inputs analog to digital converted data. performs algorithms to improve the thermal images and then outputs the corrected frame data to frame buffers for NTSC encoding and for digital outputs.. To enhance the quality of the thermal images, two point correction method is applied. Figures indicate that the corrected thermal images are much improved.

• Journal of Ocean Engineering and Technology
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• v.11 no.1
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• pp.96-96
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• 1997

This paper presents a Inertial Measuring Unit(IMU) for motion measurement of an AUV. The IMU is composed of three parts: inertial sensors with three servo accelerometers and three rate gyros, an analog/digital interface board, and a signal processing board with TMS320C31 DSP processor. The IMU is a class of strap-down inwetial navigation system does not applicable directly to the navigation system in consequence of the AUV and integrated sensors for an integrated navigation system of the AUV. Fast calculstion of direction cosine matrix for the coordinate transformation body to reference is obtained through the DSP processor. A switching algotrithm is used to lessen the low frequency drift effect of the gyros in the vertical plane with use of low pass filtering of the signal of the accelerometers.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.69-72
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• 1997

A universal controller is designed using a DSP (digital signal processor). The design objectives of the system are to implement control algorithms that require a lot of calculations and to develop a convenient user-interface environment. To demonstrate the efficiency of the system, the time delay control algorithm is implemented for the 2 D.O.F.SCARA type robot and the experimental results are presented.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• 전기의세계
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• v.32 no.5
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• pp.263-272
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• 1983

본고에서는 음성코우딩 할 때 제일 고려되어야할 음질과, 현재 많이 사용되고 있는 대표적인 음성코우딩 방식, 음성코우딩 방식을 실시간(real-time)에서 동작시키기 위해서 현재 많이 사용하고 있는 DSP(digital-signal-processor)에 대해 설명한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.45-51
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• 2000

This paper describes real-time implementation of a multi-channel G.729A speech coder using a 16 bit fixed-point Digital Signal Processor (DSP) and its application to a Voice Mailing Service (VMS) system. TMS320C549 by Texas Instruments was used as a fixed point DSP chip and a 4 channel G.729A coder was implemented on the chip. The implemented coder required 14.5 MIPS for the encoder and 3.6 MIPS for the decoder at each channel. In addition, memories required by the coder were 9.88K words and 1.69K words for code and data sections, respectively. As a result, the developed VMS system that accommodates two DSP chips was able to support totally 8 channels. Experimental results showed that the our multi-channel coder passes all of test vectors provided by ITU-T.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.380-383
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• 2001

The paper presents a cost effective and increased performance position servo system using the TMS320F240 digital signal processor (DSP) produced by Texas Instruments as microprocessor and Brushless Direct Current Motor (BLDCM) as executor. In order to make up for the drawback of conventional PID controls, the fuzzy PID is employed. The result of simulations and experiments has confirmed that the whole system is simple and reliable; the robustness of system is improved by using fuzzy PID.