• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.74-86
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• 2006

This paper proposes a robust and computationally efficient algorithm for automatic video object segmentation. For implementing the spatio-temporal segmentation, which aims for efficient combination of the motion segmentation and the color segmentation, an SOM-based hierarchical clustering method in which the segmentation process is regarded as clustering of feature vectors is employed. As results, problems of high computational complexity which required for obtaining exact segmentation results in conventional video object segmentation methods, and the performance degradation due to noise are significantly reduced. A measure of motion vector reliability which employs MRF-based MAP estimation scheme has been introduced to minimize the influence from the motion estimation error. In addition, a noise elimination scheme based on the motion reliability histogram and a clustering validity index for automatically identifying the number of objects in the scene have been applied. A cross projection method for effective object tracking and a dynamic memory to maintain temporal coherency have been introduced as well. A set of experiments has been conducted over several video sequences to evaluate the proposed algorithm, and the efficiency in terms of computational complexity, robustness from noise, and higher segmentation accuracy of the proposed algorithm have been proved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.37-47
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• 2008

Exploitation of address generation units which are typically provided in DSPs plays an important role in DSP code generation since that perform fast address computation in parallel to the central data path. Offset assignment is optimization of memory layout for program variables by taking advantage of the capabilities of address generation units, consists of memory layout generation and address pointer assignment steps. In this paper, we propose an effective address pointer assignment method to minimize the number of address calculation instructions in DSP code generation. The proposed approach reduces the time complexity of a conventional address pointer assignment algorithm with fixed memory layouts by using minimum cost-nodes breaking. In order to contract memory size and processing time, we employ a powerful pruning technique. Moreover our proposed approach improves the initial solution iteratively by changing the memory layout for each iteration because the memory layout affects the result of the address pointer assignment algorithm. We applied the proposed approach to about 3,000 sequences of the OffsetStone benchmarks to demonstrate the effectiveness of the our approach. Experimental results with benchmarks show an average improvement of 25.9% in the address codes over previous works.

• The Journal of Advanced Prosthodontics
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• v.12 no.2
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• pp.100-106
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• 2020

PURPOSE. The purpose of this in vitro study was to evaluate the fitting accuracy of single crowns made from a novel presintered Co-Cr alloy prepared with a computer-aided design and computer-aided manufacturing (CAD/CAM) technique, as compared with crowns manufactured by other digital and the conventional casting technique. Additionally, the influence of oxide layer on the fitting accuracy of specimens was tested. MATERIALS AND METHODS. A total of 40 test specimens made from Co-Cr alloy were investigated according to the fitting accuracy using a replica technique. Four different methods processing different materials were used for the manufacture of the crown copings (milling of presintered (Ceramill Sintron-group_cer_sin) or rigid alloy (Tizian NEM-group_ti_nem), selective laser melting (Ceramill NPL-group_cer_npl), and casting (Girobond NB-group_gir_nb)). The specimens were adapted to a resin model and the outer surfaces were airborne-particle abraded with aluminum oxide. After the veneering process, the fitting accuracy (absolute marginal discrepancy and internal gap) was evaluated by the replica technique in 2 steps, before removing the oxide layer from the intaglio surface of the crowns, and after removing the layer with aluminum oxide airborne-particle abrasion. Statistical analysis was performed by multifactorial analysis of variance (ANOVA) (α=.05). RESULTS. Mean absolute marginal discrepancy ranged between 20 ㎛ (group_cer_npl for specimens of Ceramill NPL) and 43 ㎛ (group_cer_sin for crowns of Ceramill Sintron) with the oxide layer and between 19 ㎛ and 28 ㎛ without the oxide layer. The internal gap varied between 33 ㎛ (group_ti_nem for test samples of Tizian NEM) and 75 ㎛ (group_gir_nb for the base material Girobond NB) with the oxide layer and between 30 ㎛ and 76 ㎛ without the oxide layer. The absolute marginal discrepancy and the internal gap were significantly influenced by the fabrication method used (P<.05). CONCLUSION. Different manufacturing techniques had a significant influence on the fitting accuracy of single crowns made from Co-Cr alloys. However, all tested crowns showed a clinically acceptable absolute marginal discrepancy and internal gap with and without oxide layer and could be recommended under clinical considerations. Especially, the new system Ceramill Sintron showed acceptable values of fitting accuracy so it can be suggested in routine clinical work.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• The KIPS Transactions:PartB
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• v.14B no.5
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• pp.329-336
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• 2007

In this paper we propose both the construction of image DB including information on the shooting location and direction of the captured outdoor images and the efficient retrieval method from the DB. Furthermore, for the automatic extraction of the location and direction information, we suggest to have the Digital Camera equipped with an expandable GPS modulo which has a function to calculate the location and direction and also to utilize GPS IFD tags in the EXIF. Then that will make it possible for us to retrieve quickly and precisely the target image with its geography and other objects on the ground included. In the previous retrieval method based only on the location, we eel some extra useless images due to the fact that all the images in the ROI(Region Of Interest) are searched on one condition, radius. However, with the proposed method in this paper, we can not only retrieve all the images selectively within the ROI but also achieve nearly 100% of precision when we search for the target images within DOI(Direction Of Interest) with another condition, direction, added. Applying this method to an image retrieval system, we can classify or retrieve natural images based on the location and direction information, which, in turn, will be vitally useful to diverse industrial fields such as disaster alarm system, fire and disaster prevention system, traffic information system, and so forth.

• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.123-130
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• 2009

Motion estimation (ME) plays an important role in digital video compression. But it limits the performance of image quality and encoding speed and is computational demanding part of the encoder. To reduce computational time and maintain the image quality, integer pel and fractional pel ME methods are proposed in this paper. The proposed method for integer pel ME uses a hierarchical search strategy. This strategy method consists of symmetrical cross-X pattern, multi square grid pattern, diamond patterns. These search patterns places search points symmetrically and evenly that can cover the overall search area not to fall into the local minimum and to reduce the computational time. The proposed method for fractional pel uses full search pattern, center biased fractional pel search pattern and the proposed search pattern. According to block sizes, the proposed method for fractional pel decides the search pattern adaptively. Experiment results show that the speedup improvement of the proposed method over Unsymmetrical cross Multi Hexagon grid Search (UMHexagonS) and Full Search (FS) can be up to around $1.2{\sim}5.2$ times faster. Compared to image quality of FS, the proposed method shows an average PSNR drop of 0.01 dB while showing an average PSNR gain of 0.02 dB in comparison to that of UMHexagonS.

• The KIPS Transactions:PartB
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• v.15B no.6
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• pp.575-584
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• 2008

According to the network condition, the communication network overload could be occurred when media transmitting. Many researches are being carried out to lessen the network overload, such as the filtering, load distributing, frame dropping and many other methods. Among these methods, one of effective method is frame dropping that reduces specified video frames for bandwidth diminution. B frames are dropped and then I, P frames are dropped according to dependency among the frames in frame dropping. This paper proposes a scheme for protecting copyrights by encryption, when we apply frame dropping to reduce bandwidth of media following MPEG-4 file format. We designed two kinds of frame dropping: first one stores and then sends the dropped files and the other drops frames in real-time when transmitting. We designed three kinds of encryption methods in which DES algorithm is used to encrypt MPEG-4 data: macro block encryption in I-VOP, macro block and motion vector encryption in P-VOP, and macro block and motion vector encryption in I, P-VOP. Based on these three methods, we implemented a digital right management solution for MPEG-4 data streaming. We compared the results of dropping, encryption, decryption and quality of video sequences to select an optimal method, and there is no noticeable difference between the video sequences recovered after frame dropping and the ones recovered without frame dropping. The best performance in encryption and decryption of frames was obtained when we apply the macro block and motion vector encryption in I, P-VOP.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of IKEEE
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• v.14 no.2
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• pp.16-23
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• 2010

Since the interest of a brain science research is increased recently, various devices using brain waves have been developed in the field of brain training game, education application and brain computer interface. In this paper, we have developed a portable EEG measurement and a bluetooth based wireless transmission device measuring brain waves from the frontal lob simply and conveniently. The low brain signals about 10~100${\mu}V$ was amplified into several volts and low pass, high pass and notch filter were designed for eliminating unwanted noise and 60Hz power noise. Also, PIC24F192 microcontroller has been used to convert analog brain signal into digital signal and transmit the signal into personal computer wirelessly. The sampling rate of 1KHz and bluetooth based wireless transmission with 38,400bps were used. The LabVIEW programing was used to receive and monitor the brain signals. The power spectrum of commercial biopac MP100 and that of a developed EEG system was compared for performance verification after the simulation signals of sine waves of $1{\mu}V$, 0~200Hz was inputed and processed by FFT transformation. As a result of comparison, the developed system showed good performance because frequency response of a developed system was similar to that of a commercial biopac MP100 inside the range of 30Hz specially.