• Journal of Broadcast Engineering
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• v.6 no.1
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• pp.66-71
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• 2001

This paper Introduces an implementation of MPEG-2 AAC codec system for digital audio broadcasting. This system consists of the encoder and the decoder. This system includes MPEG-2 system multiplexing and demultiplexing modules for Interfacing to the ETRI-DAB system. Four DSPs are adopted for the encoder and three DSPs for 7he decoder. Each DSP Processes system control. 1/0 control, audio signal processing. multiplexing and demultiplexing. This Paper also discusses some near future estimations relaxed to the DAB system and it\`s services. Currently a stereo audio codec is available but multi-channel audio codec and MPEG-4 audio cosec wall be also Implemented.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.43-48
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• 2000

This paper introduces MPEG-2 AAC codec system fur digital audio broadcasting. This system consists of encoder and decoder, and this system provides MPEG-2 system multiplexing and demultiplexing functions. Four DSPs are adopted fur encoder and three DSPs fur decoder. Each DSP processes system control, I/O control, and audio signal processing, multiplexing and demultiplexing. This paper also discusses about some near future estimations related to DAB system and services. And at the end of this paper describes about future development plans.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.117-120
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• 2005

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A,/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tass in the DBS receiver is verified by using a simple feasibility test. Then. several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.78-85
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• 1998

In this paper we propose a VLSI implementation technique for camcorder's digital zooming system. The proposed VLSI includes the system clock(CLK), vertical drive(VD), horizontal drive(HD),blank(BLK), and field(FLD) signals as inputs, and produces magnified image as an output, with 256 different magnification ratios. In general, the above mentioned input signals are provided by the CCD driving IC in most camcorders. As a result, the proposed digital zooming VLSI can magnify a part of the input image by up to 256 times, where the magnification ratio can be chosen among 256 different steps. In the application point of view, the proposed VLSI can be used in any digital camcorder for realizing near continuous step digital zooming without any additional circuitry, such as micom or a general purpose digital signal processor.

• International journal of advanced smart convergence
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• v.8 no.3
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• pp.184-192
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• 2019

The existing digital signage systems inside the elevators are a lack of tailored contents appropriate to the space and environment inside or outside the elevators. Also, they almost impossible to flexibly respond to various contents disclosure according to the demand of the consumers or the elevator markets. Therefore we design and implement an IoT(Internet of Things)-based smart digital signage system for the safety of elevator passengers.. In order to provide IoT-based information to the smart digital signage within the elevator, we propose an IoT system as a set-top box with gyroscope sensor, acceleration sensor, RFID(Radio-Frequency Identification), fine dust sensor, etc., which processes various data collected by the sensors and provides the elevator passengers with various tailored contents such as elevator driving information, environmental information inside and outside the elevator, and disaster information in addition to simple advertisement information. The proposed IoT system is a set-top box that operates the smart digital signage and has an independent information control processor based on the IoT sensors that do not depend on the elevator control system. For the proposed smart digital signage, it supports an operating system that is independent of the elevator driving service as well as the media service. So the smart signage system has a characteristic that it does not depend on the elevator control system since it is a stand-along IoT-based information control system. With the proposed system providing intuitive content for the surge, steep descent, and radical movements of an elevator due to an emergency situation, the elevator passengers should be able to recognize the situation quickly and respond accordingly. In the near future, the proposed system will expand the market of digital signage applied in conjunction with the development of contents in the disaster, safety and environment fields, and expect expected to revitalize related industries associated with signage.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.334-343
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• 2016

In this paper, we developed a low cost smart puck system that can interact with the intuitive operation of natural finger touches. The tangible smart puck, designed for capacitive tabletop display, has Arduino embedded processor which communicates only with the MT server. The MT server communicates both to the smart puck and the display server. The display server displays the relevance information on the location of the smart pucks on the tabletop display and handles interactions with the users. The experiment results show that the accuracy of identifying the smart puck ID was very reliable enough to use in practice, and the information presentation processing time is confirmed excellent enough compared to traditional expensive commercial products.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.197-200
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• 2004

디지털 TV 전송 방식중의 하나인 ATSC 8-VSB 시스템의 등화기는 훈련신호가 존재하는 구간에서 LMS 알고리즘을 사용하는 DFE 적옹 등화기가 사용된다. 그러나 LMS 알고리즘은 그 수렴속도가 느리고 수렴 후 오차 수준이 다른 적응 알고리즘에 비해 높다는 단점이 있다. 본 논문에서는 LMS 알고리즘을 사용하는 DFE의 오차 수준을 낮추기 위한 선형 등화기 구조의 전 처리부(pre-processor)를 사용하여 필터 수렴 후의 DFE의 오차수준을 기존의 DFE보다 낮추었으며 제안된, DFE 구조의 성능을 컴퓨터 모의 실험을 통해 분석하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.254-256
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• 2012

본 논문에서는 MPEG-D 오디오 서브그룹에서 진행 중인 Unified Speech and Audio Coding (USAC) 표준의 Linear Prediction Domain (LPD) 복호화기 모듈을 고정소수점 알고리즘으로 제안한다. USAC 부호화기는 두 개의 최신 음성-오디오 부호화기가 융합된 형태로, 음성 및 오디오 신호에 대하여 우수한 성능을 갖는 부호화기이다. USAC의 표준 완료와 본격적인 서비스화에 앞서서 USAC LPD 복호화기의 구조적인 특성을 분석하고, Digital Signal Processor (DSP)구현을 위한 LPD 복호화기의 고정소수점 알고리즘을 구축하는 동시에 모듈의 복잡도를 측정하고자 한다. 또한 고정소수점 알고리즘으로 구현된 LPD 복호화기와 기존의 부동소수점 복호화기의 성능을 비교하고, LPD 복호화기의 두 가지 부호화 모드에 따른 복잡도 이슈를 다루도록 한다.

• Journal of Broadcast Engineering
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• v.13 no.4
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• pp.452-462
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• 2008

In this paper, we address issues associated with the real-time implementation of the MPEG-1/2 Layer-II (or MUSICAM) and MPEG-4 ER-BSAC decoders for Digital Multimedia Broadcasting (DMB) on TMS320C64x+ that is a fixed-point DSP processor with a clock speed of 330 MHz. To achieve the real-time requirement, they should be optimized in different steps as follows. First of all, a C-code level optimization is performed by sharing the memory, adjusting data types, and unrolling loops. Next, an algorithm level optimization is carried out such as the reconfiguration of bitstream reading, the modification of synthesis filtering, and the rearrangement of the window coefficients for synthesis filtering. In addition, the C-code of a synthesis filtering module of the MPEG-1/2 Layer-II decoder is rewritten by using the linear assembly programming technique. This is because the synthesis filtering module requires the most processing time among all processing modules of the decoder. In order to show how the real-time implementation works, we obtain the percentage of the processing time for decoding and calculate a RMS value between the decoded audio signals by the reference MPEG decoder and its DSP version implemented in this paper. As a result, it is shown that the percentages of the processing time for the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders occupy less than 3% and 11% of the DSP clock cycles, respectively, and the RMS values of the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders implemented in this paper all satisfy the criterion of -77.01 dB which is defined by the MPEG standards.

• Journal of Broadcast Engineering
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• v.12 no.1 s.34
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• pp.53-60
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• 2007

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tasks in the DBS receiver is verified by using a simple feasibility test. Then, several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.