• 전기의세계
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• v.28 no.1
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• Journal of the Korean Institute of Navigation
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• v.8 no.1
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• pp.15-42
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• 1984

Many studies have been done in the field of fuzzy logic theory, but it's application to the ship's steering system is few until this date. This paper is to survey the effect of application of fuzzy logic control by new compositional rule of Inference to the ship's steering system. The controller is made up of a set of Linguistic Control Rules which are conditional linguistic statements connecting the inputs and output, and take the inputs derived from deviation angle and it's angular velocity. The Linguistic Control Rules are implemented on the digital computer to verify the performance of the fuzzy logic controller and simulations have been done in six cases of initial condition and disturbance type. Consequently, it was proved that the ship's steering system by introducing the F.L.C. is performed efficiently and less energy loss system compared with the conventional autopilot.

• Journal of Internet Computing and Services
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• v.16 no.4
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• pp.61-70
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• 2015

This paper presents a web-based Java applet for understanding the concepts in digital logic circuits and student satisfaction survey was carried out in order to show its educational validity. Through our educational Java applet, the learners will be capable of learning the concepts and principles related to digital logic circuit experiments and how to operate virtual experimental equipments and virtual bread board. The proposed educational Java applet is composed of five important components: Principle Classroom to explain the concepts and principles for digital logic circuit operations, Simulation Classroom to provide a web-based simulator to the learners, Virtual Experiment Classroom to provide interactive Java applet about the syllabus of off-line laboratory class, Assessment Classroom, and Management System. With the aid of the Management System every classroom is organically tied together collaborating to achieve maximum learning efficiency. Finally, we have obtained several affirmative effects such as high learning standard, reducing the total experimental hours and the damage rate for experimental equipments.

• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.5
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• pp.229-239
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• 1985

This paper presents the digital position control system for PM step motor using microcomputer. An algorithm is developed not only for the reduction of a lorge number of logiccircuits of the existing positon control system but also for the substitution to software for logic functions. The program to sotisfy this algorithm is studied out, which is written into the EPROM to make up the digital position control system. The justfiability of the system is proved by experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1203-1208
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• 2016

For young children who are not spontaneous or not accurate in verbal communication of their emotions and experiences, drawing is a good means of expressing their status in mind and thus drawing analysis with chromatics is a traditional tool for art therapy. Recently, children enjoy digital drawing via painting tools thus there is a growing needs to develop an automatic digital drawing analysis tool based on chromatics and art therapy theory. In this paper, we propose such an analyzing tool based on dominant color analysis. Technically, we use ART2 clustering and fuzzy logic to understand the fuzziness of subjects' status of mind expressed in their digital drawings. The frequency of color usage is fuzzified with respect to the membership functions. After applying fuzzy logic to this fuzzified central vector, we determine the dominant color and supporting colors from the digital drawings and children's status of mind is then analyzed according to the color-personality relationships based on Alschuler and Hattwick's historical researches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.131-134
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• 2002

In this work, we have developed a systematic way of utilizing the basic design tools for superconductive electronics. This include WRSPICE, XIC, margin program, and L-meter. Since the high performance analog-to- digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Single Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an 1-bit analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. Based on this circuit we performed margin calculations of the designed circuits and optimized circuit parameters. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter. Circuit inductors were adjusted according to these calculations and the final layout was obtained.

• Nuclear Engineering and Technology
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• v.52 no.10
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• pp.2339-2345
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• 2020

Radiation imaging systems consisting of a large number of channels greatly benefit from multiplexing methods to reduce the number of channels with minimizing the system complexity and development cost. In conventional pixelated radiation detector modules, such as anger logic, is used to reduce a large number of channels that transmit signals to a data acquisition system. However, these methods have limitations of electrical noise and distortion at the detector edge. To solve these problems, a multiplexing concept using a digital signal encoding technique based on a time delay method for signals from detectors was developed in this study. The digital encoding multiplexing (DEM) method was developed based on the time-over-threshold (ToT) method to provide more information including the activation time, position, and energy in one-bit line. This is the major advantage of the DEM method as compared with the traditional ToT method providing only energy information. The energy was measured and calibrated by the ToT method. The energy resolution and coincidence time resolution were observed as 16% and 2.4 ns, respectively, with DEM. The position was successfully distributed on each channel. This study demonstrated the feasibility that DEM was useful to reduce the number of detector channels.

• Journal of Internet Computing and Services
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• v.16 no.3
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• pp.33-41
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• 2015

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as web-based educational Java applets. The learners will be able to experience interesting learning process by executing the proposed Java applets. In addition, since the proposed Java applets were designed to contain educational technologies by step-by-step procedure, the maximization of learning efficiency can be obtained. The learners can make virtual experiments on the simplification of digital logic circuits by clicking on some buttons or filling out some text fields. Furthermore, the Boolean expression and its schematic diagram occurred in the simplification process will be displayed on the separate frame so that the learners can learn effectively. The schematic diagram enables them to check out if the logic circuit is correctly connected or not. Finally, since the simplification algorithm used in the proposed Java applet is based on the modified Quine-McCluskey minimization technique, the proposed Java applets will show more encouraging result in view of learning efficiency if it is used as assistants of the on-campus offline class.