• 제목/요약/키워드: Digital Logic

검색결과 673건 처리시간 0.029초

진단 수행도에 대한 지식형태의 효용에 관한 연구 (The Effects of Types of Knowledge on the Performance of Fault Diagnosis)

  • 함동한;윤완철
    • 대한산업공학회지
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    • 제22권3호
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    • pp.399-412
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    • 1996
  • With respect to the effects of types of knowledge on human diagnostic performance, the results of several experiments claimed that training with procedural knowledge is more effective than training with principle knowledge. However, more useful results would be attained by investigating when and how the principles of system dynamics is valuable for diagnosis. Accordingly, we conducted an experiment to reevaluate the value of principle knowledge in two problem situations. A simulator system, named DLD, to diagnose an electronic device was created. It is a context-free digital logic circuit which includes forty-one gates of three basic types. The experiment investigated the effects of principle knowledge over common procedural knowledge. The experimental results showed that the effects of principle knowledge is dependent on the complexity of diagnostic situations. This adds up on experimental evidence against the presumed ineffectiveness of principle knowledge and forward reasoning in fault diagnosis. The results also suggest the source of the usefulness of principle knowledge.

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경량전철용 직류배전반의 정보 전송방식 (An Information Transmission Method of the DC Switchgear for Light Railway Vehicle)

  • 이현두;김수남;류승표;이세현
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2005년도 전력전자학술대회 논문집
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    • pp.143-145
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    • 2005
  • This paper describes the transmission method of an information using communication networks between RTU(Remote Terminal Unit) and PCU(Protection and Control System) of the DC switchgear for Light Railway Vehicle. Also the test result carried out in the laboratory was represented. In this test, transmission signal waveform, polling time, response time and request/response frame between RTU and PCU were measured. The field test including the measurements of analog signal and status of the digital logic operation of PCU was conducted in Gyeongsan Test Track.

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Half-Cycle-Waveform-Inversed Single-Carrier Seven-level Sinusoidal Modulation

  • Wu, Fengjiang;Sun, Bo;Zhang, Lujie;Sun, Li
    • Journal of Power Electronics
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    • 제13권1호
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    • pp.86-93
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    • 2013
  • A half-cycle-waveform inversion based three reference modulations seven-level SPWM (TRM-SPWM) scheme with one carrier is proposed in this paper. To keep the same comparison logics for the modulations and carrier during the negative half cycle and the positive one for the modulations, in the negative half cycle of the modulations, the DC offsets related to the amplitude of the carrier are set on the three modulations, respectively. The seven-level SPWM waveform with dead time thereby is implemented with only one Digital Signal Processor (DSP) without any other attached logic circuit. The basis principle of the proposed TRM-SPWM is analyzed in detail, and the frequency spectrums of the conventional and the proposed schemes are derived and compared with each other through simulation. The DSP based implementation is presented and detailed experimental waveforms verify the accuracy and feasibility of the proposed TRM-SPWM scheme.

다출력 스위칭함수의 설계에 관한 계산기 앨고리즘 (A computer algorithm for implementing the multiple-output switching functions)

  • 조동섭;황희륭
    • 전기의세계
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    • 제29권10호
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    • pp.678-688
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    • 1980
  • This paper is concerned with the computer design of the multiple-output switching functions by using the improved MASK method in order to obtain the paramount prime implicants (prime implicants of the multiple-output switching function) and new algorithm to design the optimal logic network. All the given minterms for each function are considered as minterms of one switching function to simplify the desigh procedures. And then the improved MASK method whose memory requirement and time consuming are much less than any existing known method is applied to identify the paramount prime implicants. In selecting the irredundant paramount prime implicants, new cost criteria are generated. This design technuque is suitable both for solving a problem by hand or programming it on a digital computer.

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무철심형 선형 동기전동기의 드라이브 설계에 관한 연구 (A study on the design of driver for Lroness Linear Synchronous Motor)

  • 김상우;이재헌;김상은;김종무;이석규
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 D
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    • pp.2522-2524
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    • 2000
  • In this paper, a controller design for ironless linear synchronous motor is proposed. The designed controller is mainly composed of speed and current control, which are carried out by the high-speed digital signal processor(DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented using by 32-bit DSP(TMS32OC31), a high-integrated logic device(EPM940), and IPM(Intelligent Power Module) for compact and powerful system design. The experimental results show the effective performance of controller for careless linear synchronous motor.

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EPLD를 이용한 안전성이 고려된 NMR PPC의 보팅메카니즘 설계와 신뢰도 분석 (Design of a Voting Mechanism considering Safety for NMR PPC Using EPLD and Reliability Analysis)

  • 유동완;박희윤;구인수;서보혁
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 D
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    • pp.2557-2560
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    • 2000
  • The protection system of the nuclear reactor and chemical reactor are representative of PPC(Plant Protection Controller). This PPC must be designed based on reliability as well as concept of safety, which is a failed system go a way of safe. PPC is consist of part of data acquisition, calculator, communication with redundancy, and a voter is important factor of reliability. Because it is serial connected. This paper presents a Design and Analysis of a Voting Mechanism considering Safety for NMR PPC Using EPLD. In the case of digital implementation a coincidence logic(voter) of PPC, it needs CPU and memory, so increase a number of units. Therefore the failure rate and cost is increased. On the contrary when it is designed EPLD or FPGA.

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자기구성 퍼지 제어기법에 의한 로봇 매니퓰레이터의 지능제어에 관한 연구 (A Study on Intelligent Control of Robot Manipulator Using Self-Organization Fuzzy Control Technology)

  • 김종수;김용태;한성현
    • 한국공작기계학회:학술대회논문집
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    • 한국공작기계학회 1999년도 춘계학술대회 논문집
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    • pp.193-198
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    • 1999
  • In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules.

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Hybrid Stepping Motor의 Driving Controller 설계와 응용에 관한 연구 (A Study on Applications and Design of Driving Controller Circuit in hybrid Stepping Motor)

  • 최도순
    • 한국산업정보학회논문지
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    • 제6권2호
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    • pp.74-79
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    • 2001
  • 로봇과 자동화기기에 범용으로 사용되는 Stewing Motor의 Driving을 위하여 unipolar 방식과 bipolar 방식의 Controller Circuit를 design 하였으며 특히 design시 Digital logic을 이용하여 Controller를 설계 제작하여 실험을 통해 그 응용성을 실험하였다. 또한 Motor의 효율 향상을 위하여 Motor의 Winding에 흐르는 전류를 제어하기 위하여 constant Current Limit Methode와 Constant Voltage Limit Methode를 분석하고 실재 회로 제작 시 응용하여 Motor의 효율을 향상시켰다.

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PN Chip Clock Generator for CDMA Code Synchronization

  • Oh, Hyun-Seo
    • 한국정보통신학회논문지
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    • 제1권2호
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    • pp.193-197
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    • 1997
  • In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

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역추적 방식의 시스토릭 어레이 구조를 가진 연판정 비터비 복호기의 설계 (VLSI Design of Soft Decision Viterbi Decoder Using Systolic Array Architecture)

  • 김기보;김종태
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 G
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    • pp.3199-3201
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    • 1999
  • Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

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