• 대한기계학회논문집A
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• 제28권5호
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• pp.593-602
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• 2004

We have developed a digital control rod control system not only to improve its performance but also to improve its reliability and speed of response so that it can replace the old fashioned analog system. However, a new developed digital control system should be tested to prove the validity by using any prototype or mock-up before application. The reliability prediction and the reliability block diagram analysis methods were adopted to verify the reliability of the developed hardware. For the case of software, especially fur a new developed control algorithm it has been tested to prove performances and validation by using a dynamic simulator and mock-up of control rod drive mechanism altogether. Here we want to present some key factors regarding to the new developed digital system with some verification procedures.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제15권3호
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• pp.180-185
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• 2015

Digital infrared thermal imaging is a non-invasive adjunctive diagnostic technique that allows an examiner to visualize and quantify changes in skin surface temperature. The asymmetry of temperature differences between the diseased and the contralateral healthy body parts can be automatically analyzed and has been studied in many areas of medical science. In this paper, we propose a method for intelligent automatic asymmetry detection based on a K-means analysis and a YCbCr color model. The implemented software successfully visualizes an asymmetric distribution of colors with respect to the patients’ health status.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제11B권4호
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• pp.185-192
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• 2001

In SRM drive, the ON·OFF angles of each phase switch should be accurately controlled in order to control the torque and speed stably. The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to control the SRM power circuit, respectively. However, as the speed increases, the amount of the switching angle deviation from the preset values is also increased. Therefore, the low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper, As a result, a stable high speed SRM drive can be achieved by the high resolution switching angle control and it is verified from the experiments that the proposed encoder the logic controller can be a powerful candidate for the practical low cost SRM drive.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2002년도 춘계학술대회 논문집
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• pp.190-198
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• 2002

In switched reluctance motor(SRM) drive, it is necessary to synchronize the stator phase excitation with the rotor position. Therefore the rotor position information is an essential. Usually optical encoders or resolvers are used to provide the rotor position information. These sensors are expensive and are not suitable for high speed operation. In general, the accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor. But the region of high speed, switching angles are fluctuated back and forth from the preset values, witch are cause by the sampling period of the microprocessor. Therefore, the low cost linear encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper It is verified from the experiments that the proposed encoder and logic controller can be a powerful candidate for the practical low cost SRM drive.

• 전기학회논문지
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• 제56권1호
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• pp.106-111
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• 2007

In this study, we designed a digital fuzzy logic controller based on FPGA and microprocessor for MPPT of the sofar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessor.

• 한국멀티미디어학회:학술대회논문집
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• 한국멀티미디어학회 2001년도 추계학술발표논문집
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• pp.746-751
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• 2001

본 논문에서는 디지털 논리회로에 대하여 인터넷을 기반으로 가상교육 및 실험실습이 가능한 멀티미디컨텐츠를 개발하였다. 가상강의를 위한 컨텐츠들은 WMT 기술 및 애니메이션이 포함된 파워포인트 자료로 구성된 화상강의 모들과 개념이해를 위한 플래쉬 및 회로실험을 위한 자바 프로그램들로 구성되었다. 또한 웹 상에서의 가상 실험실을 구현하기 위해 임의의 디지털 논리회로 설계 및 검증을 위한 LogicSim 프로그램과 실험기관과 IC 칩 등을 이용한 임의회로의 가상실험 프로그램인 BreadBoard 등을 개발하였고 웹 상에서의 리포트 작성, 제출 및 검사가 가능한 Report 프로그램, 이론 학습 및 가상실험 보조 유틸리티 프로그램들을 개발하였다.

• 한국정보통신학회논문지
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• 제4권5호
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• pp.943-949
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• 2000

영상처리에 의한 물체 해석에 있어서 선의 검출은 중요한 역할을 하는데, 영상에서 선은ridge과 ravine을 검출함으로서 얻을 수 있다. 본 논문에서는 local min 및 local max 연산을 사용하여 ridge 와 ravine을 검출하는 기법을 제시한다. 본 기법은 이들 연산의 침식 및 팽창 특성을 이용하여 방향 정보를 구함이 없이 ridge와 ravine을 검출할 수 있으며, 기존의 해석적 방법에 비해 매우 단순하고 효과적인 방법이다. 실험을 통해 본 기법이 효능을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 전자공학회논문지A
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• 제30A권2호
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.