• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.131-137
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• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.4
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• pp.605-616
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• 2020

Obfuscation technology delays the analysis of a program by modifying internal logic such as data structure and control flow while maintaining the program's functionality. However, the application of such obfuscation technology to malicious code frequently occurs to reduce the detection rate of malware in antivirus software. The obfuscation technology applied to protect software intellectual property is applied to the malicious code in reverse, which not only lowers the detection rate of the malicious code but also makes it difficult to analyze and thus makes it difficult to identify the functionality of the malicious code. The study of reverse obfuscation techniques that can be closely restored should also continue. This paper analyzes the characteristics of obfuscated code with the option of Pack the Output File and Import Protection among detailed obfuscation technologies provided by VMProtect 3.4.0, a popular tool among commercial obfuscation tools. We present a de-obfuscation algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.5
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• pp.74-82
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• 2004

This paper describes the speed control of the surface-mounted permanent-magent synchronous motors (SMPMSNM) for elevator drive. The elevator motor needs to be a compact and slim type. Essentially, the proposed scheme uses a vector control algorithm for a speed and torque control and Anti-windup technique is adopted to prevent a windup phenomenon. This system is implemented using a high speed 32-bit DSP (TMS320C31-50), a high-integrated logic device FPGA(EPF10K10TI144-3) to design compactly and inexpensively. The proposed scheme is verified by the results through digital simulation and experiments for a three-phase 13.3[kW] SMPMSM as a MRL(MachineRoomLess) elevator motor in the laboratory.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.38-43
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• 2015

This paper describes a GPS signal generator that can generate multiple satellite signals in real time at the RF level. It realizes the verified software algorithm on a FPGA. The algorithm models orbits and environmental errors such as ionospheric and tropospheric multipath. The position of a simulated receiver is one of simulation parameters. The hardware which consists of a digital logic board and an analog board can generate 16 simulated satellites signals at the same time. The users can generate spoofing signals and jamming signals as well as satellite signals by using the windows-based control software. In addition, the software provides GIS-based simulation scenarios editing tools. We verified the generator by using commercial receivers. As an application, we configured generators as indoor positioning systems and tested them in a building. To improve the accuracy of indoor systems is our further study.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1303-1313
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• 2014

Dynamic behavior of the harmonic detection part of an active power filter (APF) has an essential role in filter compensation performances during transient conditions. Instantaneous power (p-q) theory is extensively used to design harmonic detectors for active filters. Large overshoot of p-q theory method deteriorates filter response at a large and rapid load change. In this study the harmonic estimation of an APF during transient conditions for balanced three-phase nonlinear loads is conducted. A novel fuzzy instantaneous power (FIP) theory is proposed to improve conventional p-q theory dynamic performances during transient conditions to adapt automatically to any random and rapid nonlinear load change. Adding fuzzy rules in p-q theory improves the decomposition of the alternating current components of active and reactive power signals and develops correct reference during rapid and random current variation. Modifying p-q theory internal high-pass filter performance using fuzzy rules without any drawback is a prospect. In the simulated system using MATLAB/SIMULINK, the shunt active filter is connected to a rapidly time-varying nonlinear load. The harmonic detection parts of the shunt active filter are developed for FIP theory-based and p-q theory-based algorithms. The harmonic detector hardware is also developed using the TMS320F28335 digital signal processor and connected to a laboratory nonlinear load. The software is developed for FIP theory-based and p-q theory-based algorithms. The simulation and experimental tests results verify the ability of the new technique in harmonic detection of rapid changing nonlinear loads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1271-1277
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• 2004

We propose a foe phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine Phase tuner Presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO for multi-carrier channel separation in cdma2000 3X multi-carrier receive system using these techniques show that the noise spectrum and mean square error (MSE) are reduced by 8.68 dB and 5.5 dB, respectively compared to those of truncation method and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.