• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of Practical Engineering Education
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• v.10 no.1
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• pp.49-56
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• 2018

Various types of SW education are being operated by universities for non-major undergraduates. And most of them focus on educating computational thinking. Following this computing education, there is a need for an educational method that implements and evaluates creative computing outcomes for each student. In this paper, we propose a method to realize SW education based on creative computing artifacts. To do this, we propose an educational method for students to implement digital logic circuit devices creatively and design SW algorithms that implement the functions of their devices. The proposed training method teaches a simple LED logic circuit using an Arduino board as an example. Students creatively design and implement two pairs of two input logic circuit devices, and design algorithms that represent patterns of implemented devices in various forms. And they design the functional extension and extended algorithm using the input device. By applying the proposed method, non-major students can gain the concept and necessity of algorithm design through creative computing artifacts.

• The Journal of Korean Association of Computer Education
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• v.10 no.6
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• pp.11-18
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• 2007

The proposed virtual laboratory system for digital logic circuits is composed of two main sessions, which are concept-learning session and virtual experiment session by virtual digital kit. During concept-learning session the learners can easily understand the important principles in the digital circuits to be performed. In addition, during virtual laboratory session the virtual experiments are performed by assembling and connecting the circuits on the virtual bread board, applying input voltages, making the output measurements, and comparing and transmitting the virtual experimental data. Every activity done during the virtual laboratory session is recorded on database and will be provided with the learners as a preliminary report form including personal information. Thus, the educators may check out the submitted preliminary report to estimate how well the learners understand the circuit operations. Finally, in order to show the validity of our virtual laboratory system we investigated and analysed the damage rate of real experimental equipment during class and assessed student performance on the five quizzes for one semester.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.51-54
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• 1992

Protection and control systems play a prominent part in avoiding power delivery interruptions and help to get a fast and secure restoration when a failure occurs. In order to meet the higher functional requirements on modern power system, protection speed, selectivity, sensitivity, dependability, and security are essential to ensure reliability. These functions on be satisfied by taking advantage of microprocessor and communication technologies, and digital protection relays (systems) have been developed and applied to real power system enhancing reliability and saving money. It is necessary to have a tool to analyze the functions and algorithms of digital relays for installing them to power system. The purpose of this study is to develop a digital relay simulation program to estimate digital relay performances during system faults. Components of digital protective relay including analog filter, sampling unit, digital filter, and relay logic are modeled in this program.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3112-3114
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• 2000

Recently. internet applications for efficient cyber education have drawn much interests. The world-wide web provides new opportunities for cyber education over the internet. In this paper, we developed the internet-based educational simulator for design and virtual experiment of the digital logic circuits. The proposed simulator provides the improved learning methods which can enhance the educational efficiency in digital theory. If the students execute the Digital simulator on the web. they can simulate in digital circuits through simple mouse manipulation. The proposed digital simulator can be used so that the students can easily understand the well-known digital principles.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.902-907
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• 1986

A real-time microprogrammable digital signal processor is designed and implemented using the bit-slice logic, a parallel multiplier, 74 series TTLs and MOS memories. A microinstruction set for the processor is defined and an application program development system is constructed. For its performance evalution, a digital filter and FFT are implemented with this digital signal processor. It is proved that this processor is faster than commrcially available single chip digital signal processors such as \ulcornerD 7720, AMI 2811, enabling very high speed digital signal processing.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• International Journal of Advanced Culture Technology
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• v.1 no.2
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• pp.7-12
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• 2013

Mobility management is an important issue in Mobile Ad Hoc Networks (MANETs) because location information of mobile nodes is frequently changed and it aggravates the performance in MANETs drastically. In this paper, we propose a fuzzy logic based mobility management scheme using group quorum system by considering the mobile nodes' locality in order to manage location information of mobile nodes in MANETs efficiently. The proposed scheme selects mobility databases adaptively from group quorum system by considering the degree of locality of a mobile node. The performance of the proposed scheme is evaluated by an analytical model and compared with that of existing mobility management scheme.