• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.309-312
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• 2001

In this paper, we proposed a system for bit stream wireless communication using audio/video infrared transceiver and implemented a circuit. The proposed transmitter system converted bit stream into analog signal format that is similar to NTSC. Then the analog signal can be transmitted by infrared spatial coupler for A/V signals. And the receiver system recover the bit stream by inverse process of transmitter.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• The KIPS Transactions:PartC
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• v.8C no.2
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• pp.164-172
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• 2001

최근 인터넷의 확산과 더불어 디지털 비디오 라이브러리(DVL : Digital Video Library) 서비스에 대한 관심이 고조되고 있다. 그러나 현재의 통신망 대역폭과 스위칭 환경 하에서는 종단간 QoS 보장하는데 많은 제약사항이 존재한다. 따라서 본 논문에서는 비디오 스트림 처리를 효율적으로 수행하여, 지연-처리율 특성을 만족할 수 있는 스트림 스위칭 구조를 제안하고 이에 대한 성능을 분석하였다. 제안된 ATM-기반 스트림 스위치는 각각 다중화되는 CBR(Constant Bit Rate) 및 VBR(Variable Bit Rate) 스트림의 QoS(Quality of Service)를 보장해야만 한다. 성능분석 결과는 제안된 스위치의 처리율이 r=4일 때 약 0.996의 값을 보였으며, 지연시간도 부하가 0.7 이하일 때 2미만으로 특정되었다. 이 결과는 제안된 구조가 적당한 입력 스트림의 그룹핑을 통하여 비디오 응용을 위한 처리율 및 지연 요구사항 QoS를 보장할 수 있음을 보여준다.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1355-1359
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• 2004

The two way subscriber transmission systems have tendency to spread its carrier frequency bandwidth or information bit rate and average bit error rate according to popularization of high speed information through the digital communication system, transmission medium and the Internet. This fact is an important incentive to realize new systems. These two way subscriber transmission systems usually use same cable or same carrier frequency bandwidth for up stream channel and down stream channel. In the systems, the disturbances of noise, crosstalk or fading affect the characteristics. Specifically, these disturbances cause the decrease of information bit rate and degradation of transmission quality. This paper proposes the improved method of their degradations using the particular feature of two way subscriber transmission systems and it makes clear proposed method is effective by theoretically and some numerical examples.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1575-1580
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• 2012

In this paper, a DVB-T2(Digital Video Broadcasting-the 2nd Generation Terrestrial) receiver is designed under a USB-type windows environment, and the baseband frames for MPEG2-TS stream(File or Ethernet Modes) are analyzed for verifying the receiver. In addition, the performance of the BICM(Bit Interleaved Coding & Modulation) module in the receiver is analyzed in terms of PLP(Physical Layer Pipe) and L1(Layer 1) signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2415-2423
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• 1999

We propose a new optical method which conceals the data of authorized persons by encryption before they are stored or compared in the pattern recognition system for security systems. This proposed security system is made up of two subsystems : a proposed optical encryption system and a pattern recognition system based on the JTC which has been shown to perform well. In this system, each image of authorized persons as a reference image is stored in memory units through the proposed encryption system. And if a fingerprint image is placed in the input plane of this security system for access to a restricted area, the image is encoded by the encryption system then compared with the encrypted reference image. Therefore because the captured input image and the reference data are encrypted, it is difficult to decrypt the image if one does not know the encryption key bit stream. The basic idea is that the input image is encrypted by performing optical XOR operations with the key bit stream that is generated by digital encryption algorithms. The optical XOR operations between the key bit stream and the input image are performed by the polarization encoding method using the polarization characteristics of LCDs. The results of XOR operations which are detected by a CCD camera should be used as an input to the JTC for comparison with a data base. We have verified the idea proposed here with computer simulations and the simulation results were also shown.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.