• 전자공학회논문지D
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• 제34D권8호
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• pp.41-51
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• 1997

The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2005년도 춘계 학술발표회 논문집
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• pp.910-915
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• 2005

In this study a series of tests(bench scale test) are carried out for increasing in strength of clayey soil by EK-Injection method. In addition, the effects of strength increase in the treated sample are measured by operating the vane shear test device during 25 days at 5 days intervals in order to estimate the effect of ground improvement caused by diffusion. The test results show that the strength increase was developed approximately double to 7 times in comparison to initial shear strength, and outstanding strength increase was created as much as 7 times while injecting the sodium silicate and phosphoric acid in anolyte and catholyte. In addition, the measured shear strength with the influence of diffusion and reduction of water-content had a tendency to converge in constant value in proportion to elapsed time. As a result of this study, strength increment developed by the influence of EK-Injection and diffusion rather than the reduction of water-content were high as 1000% on average

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 somma/kms meeting
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• pp.195-195
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• 2003

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.97-99
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• 1998

A optical phase modulator of 5Gbps was fabricated on LiNbO$_3$ by Ti diffusion for optical communications. In this Paper the pigtailing, mode patterns and insertion loss were discussed. And the device Properties of driving voltage and bandwidth were measured.

• 조명전기설비학회논문지
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• 제24권12호
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• pp.38-46
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• 2010

For the development of 100[W] stage lighting, quantitative and uniform color mixing that applied through color adopted Simple-Inverse matching so that color mixing can be possible along Black Body Locus. R,G,B(Red, Green, Blue) LED(Light Emitting Diode) arrangement through LED package character analysis, LED module, and the characteristic of device were considered for uniform color mixing. A distance changeable optical device was built to assure high uniformity and high diffusion of not only the middle of diffusion side but also the border side. Also, we developed the control power circuit that can expand up to 6 channels which are possible for quantitative color mixing, and the high uniformity and high quantified border light for color mixing control and the verification of color mixing characteristics by composing GUI(Graphical user interface) including color mixing simulator. By presenting the experimental results of light color control, we proved the usefulness of our developed border light and the proposed color mixing method.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.242-246
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• 1999

For the fabrication of fault current limiting device using HTSC thick film, YBa$_2Cu_3O_x$ superconducting thick film was formed by surface diffusion process of the Y$_2BaCUO_5$ and the mixed compound of (3BaCuO$_2$+2CuO) expected to be liquid phase above the peritectic temperature of YBa$_2Cu_3O_x$. For the surface diffusion, the compounds of 3BaCuO$_2$+2CuO mixed with binder material was patterned on Y$_2BaCUO_5$ substrate by the screen printing method. After proper sintering, the characteristics of current limit on thick film fabricated was measured. The thick film was able to limit the current from 2.8213 mA$_{rms}$nu to 4.2034 mA$_{rms}$ with 500${\omega}$ load resistance, and from 4.1831 mA$_{rms}$ to 4.2150 mA$_{rms}$ with 10${\omega}$ load resistance.

• 전기전자학회논문지
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• 제22권2호
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• pp.339-343
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• 2018

본 연구는 IGBT 구조에서 JFET 영역의 드라이브 인 확산거리 및 JFET영역의 윈도우의 크기에 따라서 항복전압과 온상태 전압강하 특성을 분석하였다. 시간은 동일하게 하면서 온도를 상승시켜 확산거리를 조정하였으며, 그 결과 항복전압은 감소되나, 온 상태 전압 강하 특성은 현저하게 좋아지는 것을 알 수 있었다. 따라서 드리프트 층의 비저항을 변화시켜 항복전압을 1440V로 고정하여 1.15V의 낮은 온 상태 전압 강하 값을 얻을 수 있었다. 따라서 본 연구결과를 토대로 Planar Gate IGBT에서는 JFET 영역의 공정 및 설계 파라미터를 효율적으로 조절한다면 같은 항복전압을 기준으로 상당히 낮은 온 상태 전압 강하 값을 확보할 수 있어, 소비전력의 측면에서 충분히 활용할 수 있을 것으로 판단된다.

• 전자공학회논문지A
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• 제29A권4호
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• pp.38-48
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• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.349-352
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• 2001

본 논문은 기가 SRAM급 이상의 초고집적을- 위한 0.1$\mu\textrm{m}$의 설계치수를 갖는 MOSFET의 게이트 영역에서 활성 부분의 면저항을 감소시키기 위해 n영역으로 비소를 이온 주입하였다. 어닐링은 급속 열처리 공정 방법과 엑시머 레이져 어닐링 방법을 이용하였으며, 극히 얕은 접합의 형성이 가능하였다. 얕은 접합 형성 깊이는 10~20nm이며, 비소의 주입량은 2$\times$$10^{14}$ $\textrm{cm}^2$이고, 레이져는 엑시머이며 소스는 KrF로 파장은 248mm로 어닐링 하였다. 극히 얕은 P/N$^{+}$ 접합 깊이가 15nm이며, 이때 1k$\Omega$/$\square$의 낮은 면저항 특성을 갖는 결과가 나타났다.