• 전기학회논문지
• /
• 제65권5호
• /
• pp.738-744
• /
• 2016

Current rating of a power cable can be calculated by the maximum allowable temperature in an insulating material considering the heat transfer from cable conductor. Therefore, it is very important to calculate the current rating using electrical equivalent circuit by calculated cable thermal circuit parameters but, it has not been fully investigated yet. In this paper, in order to determine the current rating of power cable, conventional calculation method has been reviewed considering the conductor resistance, loss factor of sheath, dielectric losses and thermal resistances based on the maximum allowable temperature of 345 kV $2500mm^2$ XLPE cable. To confirm the calculation result of the current rating, the conductor temperature should be examined whether it reaches the maximum allowable temperature by the thermal equivalent circuit of the cable. Then, utilizing EMTP (Electro-Magnetic Transient Program) which is a conventional program for electrical circuit, the thermal equivalent circuit was transformed to an electric equivalent circuit using an analogous relationship between thermal circuit and electrical circuit, and temperature condition including cable conductor, sheath, cable jacket could be calculated by the current rating of 345 kV $2500mm^2$ XLPE cable.

• 한국세라믹학회지
• /
• 제43권11호
• /
• pp.715-723
• /
• 2006

Perovskite oxide materials are very important for the electronics industry, because they exhibit promising properties. With an interest in the obvious applications, significant effort has been invested in the growth of highly crystalline epitaxial perovskite oxide thin films in our laboratory. And the desired structure of films was formed to achieve excellent properties. $Y_1Ba_2Cu_3O_{7-x}$ (YBCO) superconducting thin films were simultaneously deposited on both sides of 3 inch wafer by inverted cylindrical sputtering. Values of microwave surface resistance R$_2$ (75 K, 145 GHz, 0 T) smaller than 100 m$\Omega$ were reached over the whole area of YBCO thin films by pre-seeded a self-template layer. For implementation of voltage tunable high-quality varactor, A tri-layer structured SrTiO$_3$ (STO) thin films with different tetragonal distortion degree was prepared in order to simultaneously achieve a large relative capacitance change and a small dielectric loss. Highly a-axis textured $Ba_{0.65}Sr_{0.35}TiO_3$ (BST65/35) thin films was grown on Pt/Ti/SiO$_2$/Si substrate for monolithic bolometers by introducing $Ba_{0.65}Sr_{0.35}RuO_3$ (BSR65/35) thin films as buffer layer. With the buffer layer, the leakage current density of BST65/35 thin films were greatly reduced, and the pyroelectric coefficient of $7.6\times10_{-7}$ C $cm^{-2}$ $K^{-1}$ was achieved at 6 V/$\mu$m bias and room temperature.

• 마이크로전자및패키징학회지
• /
• 제6권4호
• /
• pp.41-48
• /
• 1999

실리카는 에폭시를 기지재로 하는 전자봉지재의 충진제로써 널리 사용되고 있는 재료이나 이의 낮은 방열성으로 인해 고방열성을 요구하는 부분에는 적용이 어렵다. 충진제 입자들의 지름비를 조합함으로써 최대충진 밀도를 높혀 고충진을 가능하게 하며 유동성도 향상된다는 점을 고려하여 높은 유동성을 가진 결정성 실리카(crystalline silica)를 큰 입자로 하고, 높은 열전도도와 낮은 열팽창계수를 가지지만 상대적으로 고각인 AlN을 작은 입자로 선정하여 혼합충진에 따른 EMC의 물성을 평가하였다. 실리카/AlN의 혼합비에 따른 EMC의 물성측정 결과, AlN의 투입분율을 0.3으로 하였을 때가 AlN의 투입에 따른 물성향상 효과가 가장 뛰어남을 확인 할 수 있었다. 따라서 AlN을 결정성 실리카와 최대 충진밀도에서 혼합하여 EMC에 적용할 경우에, 유동성의 저하없이 AlN의 소량투입만으로 뚜렷한 물성향상 효과를 얻을 수 있음을 확인할 수 있었다.

• Journal of Industrial and Engineering Chemistry
• /
• 제68권
• /
• pp.399-405
• /
• 2018

We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.

• 한국초전도ㆍ저온공학회논문지
• /
• 제23권3호
• /
• pp.51-54
• /
• 2021

The DC system has less power loss compared to the AC system because there is no influence of frequency and dielectric loss. However, the zero-crossing point of the current is not detected in the event of a short circuit fault, and it is difficult to interruption due to the large fault current that occurs during the opening, so the reliability of the DC breaker is required. As a solution to this, an LC resonance DC circuit breaker combined a superconducting element has been proposed. This is a method of limiting the fault current, which rises rapidly in case of a short circuit fault, with the quench resistance of the superconducting element, and interruption the fault current passing through the zero-crossing point through LC resonance. The superconducting current limiting element combined to the DC circuit breaker plays an important role in reducing the electrical burden of the circuit breaker. However, at the beginning of a short circuit fault, superconducting devices also have a large electrical burden due to large fault currents, which can destroy the element. In this paper, the reactor is connected to the source side of the circuit using PSCAD/EMTDC. After that, the change of the fault current according to the reactor capacity and the electrical burden of the superconducting element were confirmed through simulation. As a result, it was confirmed that the interruption time was delayed as the capacity of the reactor connected to the source side increased, but peak of the fault current decreased, the zero-crossing point generation time was shortened, and the electrical burden of the superconducting element decreased.

• 전기전자학회논문지
• /
• 제26권3호
• /
• pp.500-505
• /
• 2022

본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm²/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm²/Vs의 높은 전하이동도를 가졌다.

• 한국항행학회논문지
• /
• 제26권6호
• /
• pp.510-515
• /
• 2022

본 논문에서는 마이크로리터 부피의 에탄올 수용액 농도를 검출하기 위한 마이크로스트립 패치 센서 안테나를 제안하였다. 비유전율 변화에 대한 감도를 높이기 위해 패치의 방사 모서리에 직사각형 슬롯을 추가하였다. 높은 비유전율과 높은 손실 탄젠트를 가지는 극성 액체인 에탄올 수용액을 패치에 놓으면 발생하는 낮은 입력 저항을 개선하기 위해 1/4 파장 임피던스 변환기를 50 오옴 급전선과 패치 사이에 추가하여 0.76 mm 두께의 RF-35 기판에 안테나를 제작하였다. 원통형 용기를 아크릴로 제작하여 15 마이크로리터 부피의 에탄올 수용액을 에탄올 농도 0% ~ 100%까지 20% 농도 간격으로 만들어 실험하였다. 실험 결과, 에탄올 수용액의 에탄올 농도가 0%에서 100%로 증가할 때 공진 주파수가 1.947 GHz에서 2.509 GHz로 증가하여 농도검출 센서로서의 성능을 입증하였다.

• 한국군사과학기술학회지
• /
• 제27권3호
• /
• pp.311-318
• /
• 2024

In this paper, a design for a radio frequency(RF) and infrared(IR) absorber with metasurfaces is discussed in microwave frequency bands. The RF absorber includes double layers of metasurfaces to operate in S- and X-bands. Effects of sheet resistance of the metasurfaces and thicknesses of dielectric supporting layers on reflection responses are investigated. An IR stealth layer incorporates an array of conductive grids with slits to reflect IR signals but to transmit RF signals and visible rays. Periodicity of the grids and slits is studied for transmission responses in the X-band and a surface area ratio. Reflection responses of the RF/IR multispectral absorber are found to be lower than -10 dB and -16 dB in the S- and X-bands, respectively, from full-wave simulation. Finally, the RF/IR multispectral absorber is fabricated and its reflection responses are measured to verify designed performance.

• 한국산학기술학회논문지
• /
• 제21권5호
• /
• pp.516-522
• /
• 2020

수트리의 진행과정은 십수년이 걸리며 보통 매우 오래된 지중케이블에서 발견된다. 이러한 지중케이블들은 이미 접근이 어려운 곳에 있어 수트리를 검출하기 위해서는 많은 비용과 시간이 소요된다. 이러한 지중케이블의 유지보수 비용과 시간을 절감하기 위해서는 수트리가 진행된 지중케이블이 전력망에 미치는 영향을 분석할 수 있는 수학적 모델링이 필요하고, 이를 이용한 수트리 탐지 기술개발이 매우 필요한 실정이다. 본 논문에서는 수트리가 포함된 XLPE 케이블 대한 수학적 모델링을 하고자 수트리의 복잡한 구조를 Vented tree의 확인된 특정 패턴 2가지를 기준으로 가정하여 단순화 하였다. 그리고 수트리의 발달에 따른 케이블 절연층의 캐패시턴스 및 레지스턴스를 계산 및 분석하기 위해 matlab으로 시뮬레이션을 실시하였으며, 모델링의 유용성을 검증하기 위해서 참고문헌 Burkes 논문의 케이블 데이터를 동일하게 적용하였다. 시뮬레이션 결과, 캐패시턴스 크기의 변화는 케이블에 수트리 영역이 절연층에 95%까지 진행되었을 때 정상대비 약 0.025×10^-13[Farads/mm] 증가됨을 확인하였다. 레지스턴스 값의 경우 정상대비 약 0.5×10¹⁶[ohm/m] 정도 감소되는 것을 확인하였다. 따라서, Burkes 논문의 물리적 모델링 시뮬레이션 결과와 비교하였을 때 그 변화값이 매우 유사하여 본 논문에서 제시한 수학적 모델링의 유용성을 검증하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.10-10
• /
• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.