• Journal of Sensor Science and Technology
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• v.4 no.3
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• pp.80-88
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• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.

• Journal of the Korean Ceramic Society
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• v.49 no.5
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• pp.475-483
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• 2012

High capacitance X5R MLCCs based on $BaTiO_3$ ceramic dielectric layers exhibit a single broad, asymmetric arc shape impedance and modulus response over the wide frequency range between 1 MHz to 0.01 Hz. Analysis according to the conventional brick-layer model for polycrystalline conductors employing a series connection of multiple RC parallel circuits leads to parameters associated with large errors and of little physical significance. A new parametric impedance model is shown to satisfactorily describe the experimental spectra, which is a parallel network of one resistor R representing the DC conductivity thermally activated by 1.32 eV, one ideal capacitor C exactly representing bulk capacitance, and a constant phase element (CPE) Q with complex capacitance $A(i{\omega})^{{\alpha}-1}$ with ${\alpha}$ close to 2/3 and A thermally activated by 0.45 eV or ca. 1/3 of activation energy of DC conductivity. The feature strongly indicate the CK1 model by J. R. Macdonald, where the CPE with 2/3 power-law exponent represents the polarization effects originating from mobile charge carriers. The CPE term is suggested to be directly related to the trapping of the electronic charge carriers and indirectly related to the ionic defects responsible for the insulation resistance degradation.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.6
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• pp.618-629
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• 2001

This paper presents a result of failure analysis and reliability evaluation for high voltage ceramic capacitors. The failure modes and failure mechanisms were studied in two ways in order to estimate component life and failure rate. The causes of failure mechanisms for zero resistance phenomena under withstanding voltage test in high voltage ceramic capacitors molded by epoxy resin were studied by establishing an effective root cause failure analysis. Particular emphasis was placed on breakdown phenomena at the ceramic-epoxy interface. The validity of the results in this study was confirmed by the results of accelerated testing. Thermal cycling test for high voltage ceramic capacitor mounted on a magnetron were implemented. Delamination between ceramic and epoxy, which might cause electrical short in underlying circuitry, can occur during curing or thermal cycle. The results can be conveniently used to quickly identify defective lots, determine $B_{10}$ life estimation each lot at the level of inspection, and detect major changes in the vendors processes. Also, the condition for dielectric breakdown was investigated for the estimation of failure rate with load-strength interference model.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.35-36
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• 2008

PTC thermistor are characterized by an increase in the electrical resistance with temperature. The PTC materials of middle Curie point were produced or that of high Curie point (above $200^{\circ}C$), it was determined that compositional modifications of $Pb^{2+}$ for $Ba^{2+}$ produce change sin the Curie point to higher temperature. PTC ceramic materials with the Curie point above $120^{\circ}C$ were prepared by adding $PbTiO_3$, PbO or $Pb_3O_4$ into $BaTiO_3$. Thereby, adding $Pb^{2+}$ into $BaTiO_3$-based PTC material to improve Tc was studied broadly, however, weal know that PbO was poisonous and prone to volatilize, then to pollute the circumstance and hurt to people, so we should dope other innocuous additives instead of lead to increase Tc of composite PTC material. In order to prepare lead-free $BaTiO_3$-based PTC with middle Curie point, the incorporation on $Bi_{1/2}K_{1/2}TiO_3$ into $BaTiO_3$-based ceramics was investigated on samples containing 0, 1, 2, 3, 4, and 50mol% of $Bi_{1/2}K_{1/2}TiO_3$. $Bi_{1/2}K_{1/2}TiO_3$ was compounded as standby material by conventional solid-state reaction technique. The starting materials were $Bi_2O_3$, $K_2CO_3$, $BaCO_3$ and $TiO_2$ powder, and using solid-state reaction method, too. The microstructures of samples were investigated by SEM, DSC, XRD and dielectric properties. Phase composition and lattice parameters were investigated by X-ray diffraction.

• Journal of the Korean Society for Nondestructive Testing
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• v.32 no.4
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• pp.393-400
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• 2012

In recent years, nano-structured thin film systems are often applied in industries such as MEMS/NEMS device, optical coating, semiconductor or like this. Thin films are used for many and varied purpose to provide resistance to abrasion, erosion, corrosion, or high temperature oxidation and also to provide special magnetic or dielectric properties. Quite a number of articles to evaluate the characterization of thin film structure such as film density, film grain size, film elastic properties, and film/substrate interface condition were reported. Among them, the evaluation of film adhesive to substrate has been of great interest. In this study, we fabricated the polymeric thin film system with different adhesive conditions to evaluate the adhesive condition of the thin film. The nano-structured thin film system was fabricated by spin coating method. And then V(z) curve technique was applied to evaluate adhesive condition of the interface by measuring the surface acoustic wave(SAW) velocity by scanning acoustic microscope(SAM). Furthermore, a nano-scratch technique was applied to the systems to obtain correlations between the velocity of the SAW propagating within the system including the interface and the shear adhesive force. The results show a good correlation between the SAW velocities measured by acoustic spectroscope and the critical load measured by the nano-scratch test. Consequently, V(z) curve method showed potentials for characterizing the adhesive conditions at the interface by acoustic microscope.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.362-362
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• 2014

Atomic layer deposition (ALD) can be regarded as a special variation of the chemical vapor deposition method for reducing film thickness. ALD is based on sequential self-limiting reactions from the gas phase to produce thin films and over-layers in the nanometer scale with perfect conformality and process controllability. These characteristics make ALD an important film deposition technique for nanoelectronics. Tantalum pentoxide ($Ta_2O_5$) has a number of applications in optics and electronics due to its superior properties, such as thermal and chemical stability, high refractive index (>2.0), low absorption in near-UV to IR regions, and high-k. In particular, the dielectric constant of amorphous $Ta_2O_5$ is typically close to 25. Accordingly, $Ta_2O_5$ has been extensively studied in various electronics such as metal oxide semiconductor field-effect transistors (FET), organic FET, dynamic random access memories (RAM), resistance RAM, etc. In this experiment, the variations of chemical and interfacial state during the growth of $Ta_2O_5$ films on the Si substrate by ALD was investigated using in-situ synchrotron radiation photoemission spectroscopy. A newly synthesized liquid precursor $Ta(N^tBu)(dmamp)_2$ Me was used as the metal precursor, with Ar as a purging gas and $H_2O$ as the oxidant source. The core-level spectra of Si 2p, Ta 4f, and O 1s revealed that Ta suboxide and Si dioxide were formed at the initial stages of $Ta_2O_5$ growth. However, the Ta suboxide states almost disappeared as the ALD cycles progressed. Consequently, the $Ta^{5+}$ state, which corresponds with the stoichiometric $Ta_2O_5$, only appeared after 4.0 cycles. Additionally, tantalum silicide was not detected at the interfacial states between $Ta_2O_5$ and Si. The measured valence band offset value between $Ta_2O_5$ and the Si substrate was 3.08 eV after 2.5 cycles.

• Fire Science and Engineering
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• v.31 no.6
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• pp.91-98
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• 2017

The present paper is a study on the tracking characteristics depending on accelerated degradation of PVC insulation material. In order to insulation degradation of PVC insulation material, the Arrhenius equation, a type of accelerated degradation test formula, was used to conduct accelerated degradation experiments with experiment samples prepared at the following age equivalents: 0, 10, 20, 30 and 40 years. Afterwards, a tracking experiment was conducted on the accelerated experiment samples as part of the KS C IEC 60112 criteria. When measuring the PVC tracking features according to the accelerated aging, the results showed that when 0.1% of ammonium chloride was added to the PVC insulating material, but no tracking occurred. However, depending on the age equivalent, The results of analyzing the current waveform and voltage waveform of the tracking propagation process showed the age equivalent from 0 years to 40 years displayed a break down in insulation resistance and even the BDB(before dielectric breakdown) sections did not maintain the same functionality of the original material. Based on a criterion of an age equivalent of 0 years, material with an age equivalent of 10 years posed a 1.4 times greater risk, material with an age equivalent of 20 years posed a 2 times greater risk, material with an age equivalent of 30 years posed a 4.6 times greater risk, and material with an age equivalent of 40 years posed a 7 times greater risk.

• Fire Science and Engineering
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• v.30 no.4
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• pp.121-127
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• 2016

This study analyzed the structural and electrical characteristics of an iron fittings type Corrugated Stainless Steel Tubing (CSST) damaged by the Primary Current Injection Test System (PCITS). CSST consists of cladding, tube, nuts, clamp ring, flare cap, socket, and ball valve. For an evaluation of the dielectric withstand voltage, the area between the live part and non-live part of the CCST shall withstand a voltage of 220 V AC for one minute. For an evaluation of the insulation performance by 500 V DC, it is required that the insulation exceed more than $1M{\Omega}$ before the temperature rise test, $0.3M{\Omega}$ after the test. Although the average resistance of the product was $11.5m{\Omega}$, that of the product damaged at a current of 130 A by the PCITS was $11.50m{\Omega}$. Furthermore, parts of the cladding were melted and black smoke appeared when a current of 130 A applied for 10 s. After 60 s, most parts were heated and turned red. At 120 s, the parts that turned red had widened. Although it did not form a normal distribution because the P value was 0.019 with a confidential interval of 95%, it revealed outstanding characteristics with an AD (Anderson-Darling) value of 0.896 and a standard deviation of 0.5573.