• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.207-208
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• 2007

Epoxy resin insulators show a lot of advantages for electrical power apparatus. Because epoxy resin provide electrical and mechanical characteristic which is excellent, it is desirable to apply epoxy resin as a spacer and post insulation in Gas Insulated Switchgear (GIS). In this study, we have investigated the influence of surface electric field attached particle contaminated spacer surfaces under SF6 gas. Also, we performed analysis of electric field. As a result, when the particle was attached on spacer, we found out a surface electric field of characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.861-864
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• 2000

Ferroelectric thin film capacitors with high dielectric constant are important for the application of memory devices. In this work, thin films of PLT(28)(Pb$\sub$0.72/La$\sub$0.28/Ti$\sub$0.93/O$_3$) were fabricated on Pt/Ti/SiO$_2$/Si substrates in-situ annealing and ex-situ annealing have been compared depending on the annealing time. We have systematically investigated the variation of grain sizes depending on the condition of post-annealing and the variation of deposition rate. C-V measurement, ferroelectric properties, leakage current and SEM were performed to investigate the electrical properties and the microstructural properties of Pb(La,Ti)O$_3$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.389-392
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.184-187
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) lyaer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2-CMP$ process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis or used slurry.

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• Transactions on Electrical and Electronic Materials
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• v.4 no.3
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• pp.34-37
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• 2003

[ $HfO_2$ ] and $HfO_xN_y$ films were deposited by plasma-enhanced chemical vapor deposition using $Hf[OC(CH_3)_3]_4$ as the precursor in the absence of $O_2$. The crystallization temperature of the $HfO_xN_y$ films is higher than that of the $HfO_2$ film. Nitrogen incorporation in $HfO_xN_y$ was confirmed by auger electron spectroscopy analysis. After post deposition annealing (PDA) at 800$\Box$, the EOT increased from 1.34 to 1.6 nm in the $HfO_2$ thin films, whereas the increase of EOT was suppressed to less than 0.02 nm in the $HfO_xN_y$. The leakage current density decreased from 0.18 to 0.012 $A/cm^2$ with increasing PDA temperature in the $HfO_2$ films. But the leakage current density of $HfO_xN_y$ does not vary with increasing PDA temperature because an amorphous $HfO_xN_y$ films suppresses the diffusion of oxygen through the gate dielectric.

• Korean Journal of Materials Research
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• v.27 no.11
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• pp.590-596
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• 2017

We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.167-169
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• 2009

We have carried out quantitative structure and property analysis of the nanoporous structures of low dielectric constant (low-k) carbon-doped silicon oxide (SiCOH) films, which were deposited with plasma enhanced chemical vapor deposition (PECVD) using vinyltrimethylsilane (VTMS), divinyldimethylsilane (DVDMS), and tetravinylsilane (TVS) as precursor and oxygen as an oxidant gas. We found that the SiCOH film using VTMS only showed well defined spherical nanopores within the film after thermal annealing at $450^{\circ}C$ for 4 h. The average pore radius of the generated nanopores within VTMS SiCOH film was 1.21 nm with narrow size distribution of 0.2. It was noted that thermally labile $C_{x}H_{y}$ phase and Si-$CH_3$ was removed to make nanopore within the film by thermal annealing. Consequently, this induced that decrease of average electron density from 387 to $321\;nm^{-3}$ with increasing annealing temperature up to $450^{\circ}C$ and taking a longer annealing time up to 4 h. However, the other SiCOH films showed featureless scattering profiles irrespective of annealing conditions and the decreases of electron density were smaller than VTMS SiCOH film. Because, with more vinyl groups are introduced in original precursor molecule, films contain more organic phase with less volatile characteristic due to the crosslinking of vinyl groups. Collectively, the presenting findings show that the organosilane containing vinyl group was quite effective to deposit SiCOH/$C_{x}H_{y}$ dual phase films, and post annealing has an important role on generation of pores with the SiCOH film.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.190-194
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• 2003

Dielectric thin films of (P $b_{0.72}$,L $a_{0.28}$) $Ti_{0.93}$ $O_3$ (PLT(28)) have been deposited on Pt(111)/Ti/ $SiO_2$/Si(100) substrates in-situ by pulsed laser deposition using different annealing and deposition Processes. We have investigated the effect of hydrogen annealing on the ferroelectric properties of PLT thin films and found that the annealing process causes the diffusion of hydrogen into the ferroelectric film resulting in the destruction of polarization. We have tried to form the film by a two-step deposition process In order to improve electrical property. Two-step process to grow PLT films was adopted and verified to be useful to enlarge the grain size of the film and to reduce the leakage current characteristics. Structural properties and electrical properties including dielectric constant, ferroelectric characteristics, and leakage current of PLT thin films were shown to be strongly influenced by grain size. The film deposited by using two-step Process including pre-annealing treatment has a strongly(111) orientation. However, the films deposited by using single -step process with hydrogen annealing process show the smallest grain size. The film deposited by using two-step process including pre-annealing treatment shows the leakage current density of below 10$^{-7}$ A/c $m^2$ for the field of smaller than 100 kV/cm. However, the films deposited by using single-step process with hydrogen annealing process and pre-annealing process show worse leakage current density than the film deposited by using two-step process including pre-annealing treatment.tment.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.