• Title/Summary/Keyword: Device Simulation

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Simulation Study on the Safety of a Fastening Device of Agricultural By-product Collector (동역학 시뮬레이션을 통한 농업부산물 수집기 체결장치의 안전성 분석)

  • Jeong-Hun Kim;Seok-Joon Hwang;Ju-Seok Nam
    • Journal of Drive and Control
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    • v.20 no.3
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    • pp.42-49
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    • 2023
  • In this study, the safety of fastening device for the agricultural by-product collector was evaluated according to the driving ground conditions by deriving the stress, static safety factor, and fatigue life using dynamic simulation. A 3D modeling of agricultural by-product collector was carried out, and simulation model was developed by applying the material properties. As a result of dynamic simulation, the magnitude of the maximum stress generated in the fastening device was the highest when driving on the flat off-road, followed by sloped pave-road and flat pave-road. Static safety factor and fatigue life were the highest when driving on the flat pave-road, followed by sloped pave-road and flat off-road. The safety of fastening device was confirmed that static safety factor was more than 1.0 and service life exceeded 9 years in all driving ground conditions.

The Study of Circuit Model Parameter Generation Using Device Simulation (소자 시뮬레이션을 이용한 Circuit Model Parameter 생성에 대한 연구)

  • 이흥주
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.4 no.3
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    • pp.177-182
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    • 2003
  • In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.

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A development of the 3-dimensional stationary drift-diffusion equation solver (3차원 정상상태의 드리프트-확산 방정식의 해석 프로그램 개발)

  • 윤현민;김태한;김대영;김철성
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.8
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    • pp.41-51
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    • 1997
  • The device simulator (BANDIS) which can analyze efficiently the electrical characteristics of the semiconductor devices under the three dimensional stationary conditions on the IBM PC was developed. Poisson, electon and hole continuity equations are discretized y te galerkin method using a tetrahedron as af finite element. The frontal solver which has exquisite data structures and advanced input/output functions is dused for the matrix solver which needs the highest cost in the three dimensional device simulation. The discretization method of the continuity equations used in BANDIS are compared with that of the scharfetter-gummel method used in the commercial three-dimensional device. To verify an accuracy and the efficiency of the discretization method, the simulation results of the PN junction diode and the BJT from BANDIS are compared with those of the commercial three-dimensiional device simulator such as DAVINCI. The maximum relative error within 2% and the average number of iterations needed for the convergence is decreased by more than 20%. The total simulation time of the BJT with 25542 nodes is decreased to about 60% compared with that of DAVINCI.

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A Study on Converter Circuit Analysis Using GTO Device Modeling (GTO DEVICE의 MODELING에 의한 변환 회로 해석)

  • Seo, Young-Soo;Sung, Dae-Yong;Cho, Moon-Taek;Lee, Sang-Bong
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1016-1018
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    • 1992
  • A numerical model of a three junction device is presented. It allows the simulation of the external characteristics of the PNPN family devices and in this work the simulation of gate turn-off thyristor(GTO) is particularly considered. The proposed PNPN device simulation model solves all the drawbacks presented by the previous work, simulates the GTO well, and fulfills.

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The Insulation Design of Enclosure for Diagnostic Device in Extra High Voltage Line (초고압 선로 진단장치용 외함 절연설계)

  • Kim, Ki-Joon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.3
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    • pp.201-207
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    • 2015
  • In this paper, in order to avoid equipment malfunction due to electromagnetic waves, which can occur when high-voltage live line diagnostic device fabrication, the enclosure structure of the diagnostic device with power lines that can minimize the EMI (electromagnetic interference) was modeled using the FEM (finite element method). Simulation examined the strength of the electric field in the required thickness, material and regions where there is a control board while changing the curvature radius of the corner making the enclosure, and By applying a mechanical design and simulation results that occur during the actual production has been designed for the final design. Most of the simulation results for the electric field is concentrated in the final model, the inner edge of the enclosure could be confirmed that the stable structure.

Effect of Double Grid Cathode in IEC Device (IEC 장치에서 이중 그리드 음극의 영향)

  • Ju, Heung-Jin;Kim, Bong-Seok;Hwang, Hwui-Dong;Park, Jeong-Ho;Ko, Kwang-Cheol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.51-51
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    • 2010
  • We have proposed a new configuration for the improvement of neutron yield without the application of external ion sources in an inertial electrostatic confinement (IEC) device. The application of a double grid cathode to the IEC device is expected to generate a higher ion current than a single grid cathode. This paper verifies the effect of the double grid cathode by both fluid and particle simulation. Through the fluid simulation the optimal shape and applied voltage of the double grid cathode is determined, and through the particle simulation the usefulness of that is confirmed.

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Simulation of Miniaturized n-MOSFET based Non-Isothermal Non-Equilibrium Transport Model (디바이스 시뮬레이션 기술을 이용한 미세 n-MOSFET의 비등온 비형형장에 있어서의 특성해석)

  • Choi, Won-Cheol
    • Journal of the Korean Society of Industry Convergence
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    • v.4 no.3
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    • pp.329-337
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    • 2001
  • This simulator is developed for the analysis of a MOSFET based on Thermally Coupled Energy Transport Model(TCETM). The simulator has the ability to calculate not only stationary characteristics but also non - stationary characteristics of a MOSFET. It solves basic semiconductor devices equations including Possion equation, current continuity equations for electrons and holes, energy balance equation for electrons and heat flow equation, using finite difference method. The conventional semiconductor device simulation technique, based on the Drift-Diffusion Model (DDM), neglects the thermal and other energy-related properties of a miniaturized device. I, therefore, developed a simulator based on the Thermally Coupled Energy Transport Model (TCETM) which treats not only steady-state but also transient phenomena of such a small-size MOSFET. In particular, the present paper investigates the breakdown characteristics in transient conditions. As a result, we found that the breakdown voltage has been largely underestimated by the DDM in transient conditions.

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Optimization Study on the Epitaxial Structure for 100nm-Gate MHEMTs with InAlAs/InGaAs/GaAs Heterostructure (InAlAs/InGaAs/GaAs 100 nm-게이트 MHEMT 소자의 에피 구조 최적화 설계에 관한 연구)

  • Son, Myung-Sik
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.4
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    • pp.107-112
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    • 2011
  • This paper is for improving the RF frequency performance of a fabricated 100nm ${\Gamma}$-gate MHEMT, scaling down vertically for the epitaxy-structure layers of the device. Hydrodynamic simulation parameters are calibrated for the fabricated MHEMT with the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure grown on the GaAs substrate. With these calibrated parameters, simulations for the vertically-scaled epitaxial layers of the device are performed and analyzed for DC/RF characteristics, including the quantization effect due to the thickness reduction of InGaAs channel layer. A newly designed epitaxy-structure device shows higher extrinsic transconductance, $g_m$ of 1.556 S/mm, and higher frequency performance, $f_T$ of 222.5 GHz and $f_{max}$ of 849.6 GHz.

A Study on Designing a Proper External Shading Device to Diminish the Cooling Load of a Transparent Glazing Office Building (투명 유리 사무소 건물의 냉방부하 감소를 위한 적정 외부차양 배치에 관한연구)

  • Yim, Sang-Joon;Seo, Hye-Soo;Kim, Byung-Seon
    • KIEAE Journal
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    • v.2 no.4
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    • pp.21-26
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    • 2002
  • Modem architecture represent a great capitalistic, polishing, high-technology image to the public by design. As a result, glass architecture which show 'transmittance' in desinging play a leading part, consequently a role of machine is increasing in controlling an internal environment of building. These movement look like assisting an universal standard building disregarding a each nation's climate peculiarity, if glass building is applied by a proper external shading device. the shading device has a great effect on the reduction of cooling load energy, this research to propose the proper designing scheme of the fixed external shading device. The effect of proper external shading device on the cooling load is evaluated by the numeric simulation.

Development of a Real-Time Simulation Algorithm of HTS Power Cable using HTS Wire (고온초전도선을 이용한 초전도전력케이블의 실시간 시뮬레이션 알고리즘 개발)

  • Kim Jae-Ho;Park Min-Won;Cho Jeon-Wook;Sim Ki-Deok;Yu In-Keun
    • Progress in Superconductivity and Cryogenics
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    • v.8 no.3
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    • pp.54-58
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    • 2006
  • In this paper, authors developed a real-time simulation algorithm for the power device application of HTS(High Temperature Superconducting) wire by using Real Time Digital Simulator(RTDS). At present, in order to extend the power capacity of some area where has a serious problem of power quality. especially metropolitan complex city, there are so many problems such as right of way for power line routes. space for downtown substations. and the environmental protection, etc. HTS technology can be useful to overcome this problem. Recently, according to the advanced HTS technology, the power application is being researched well. Simulation is required for safety before installation of HTS power cable, a fabrication model used at the power system simulation. This paper describes a real time digital simulation method for the application of HTS wire to power device. For the simulation analysis, test sample of HTS wire was actually manufactured. And the transient phenomenon of the HTS wire was analysed in the simulated utility power grid. This simulation method is the world first trial in order to obtain much better information for installation of HTS power device into a utility network.