• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 추계종합학술대회
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• pp.196-199
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• 2000

본 논문에서는 K-대역 무궁화 위성의 하향변환기용 저잡음 증폭기를 설계하였다. 30dB이상의 높은 이득을 필요로 하는 하향변환기용 저잡음증폭기의 특성을 만족시키기 위해 3단으로 구성하였다. 설계된 3단 저잡음 중폭기에 대해 모의 실험한 결과 입력신호의 동작 주파수 19.2㎓∼20.2㎓에서 33dB의 이득과 0.93dB의 잡음지수를 보였으며, 제작 측정한 결과 이득은 25dB, 잡음지수는 1.5dB를 보였다. 한편 이 중폭기의 입·출력 반사계수는 각각 -25dB와 -28dB로 나타났고, 입·출력 정재파비는 1.5 이하로 K-대역 무궁화위성의 하향변환기용 저잡음증폭기로써의 성능을 만족할 수 있었다.

• 한국의류학회지
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• 제46권4호
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• pp.613-623
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• 2022

This study developed a functional prototype jacket designed to reduce loads on the upper extremities of workers performing repetitive motions in the same posture for extended periods of time. Dynamic taping lines were applied to the upper extremities, and three dimensional (3D) supporters were inserted in the abdomen and back waist areas corresponding to the core muscles. Clothing pressure on the upper-extremity dynamic taping lines was set to two levels (proto P1 and proto P2), and the 3D supporters were designed in three types (proto FW, proto FW/BW, proto FW/BW/BBX). According to the subjective pressure perceived on each part of the upper extremities, the level proto P1 pressure was preferred. The proto FW/BW/BBX 3D supporter was rated as excellent, and the perceived pressure was ranked as satisfactory. The prototype jacket performed upper-extremity load reduction when the upper-extremity clothing-pressure level was set to 1.8 kPa, 2.1 kPa, and 2.4 kPa on the upper arm, forearm, and wrist regions, respectively, and when 3D supporters were installed in the abdomen and back of the waist with the addition of a back band.

• International Journal of Internet, Broadcasting and Communication
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• 제10권1호
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• pp.23-30
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• 2018

Many practitioners in educational field, recently, are seeking to improve Computational Thinking through SW education. The purpose of this paper was, for promotion of SW education, to design the STEAM education process utilizing 3D printer. The project-based education process emphasized the cooperation in the process of producing common results and proposed a new STEAM education process. The designed products are expected to be used in the elementary school classes by linking with the camp and teacher training programs and the curriculum.

• 전자공학회논문지A
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• 제31A권3호
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• Journal of information and communication convergence engineering
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• 제19권2호
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• pp.73-78
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• 2021

As interest in beauty has increased, various studies have been conducted, and related companies have considered the anthropometric data handled between humans and interfaces as an important factor. However, owing to the nature of 3D human body scanners used to extract anthropometric data, it is difficult to accurately analyze a user's body shape until a service is provided because the user only scans and extracts data. To solve this problem, the body shape of several users was analyzed, and the collected anthropometric data were obtained using a 3D human body scanner. After processing the extracted data and the anthropometric data, a custom deep learning model was designed, the designed model was learned, and the user's body shape information was predicted to provide a service suitable for the body shape. Through this approach, it is expected that the user's body shape information can be predicted using a 3D human body scanner, based upon which a beauty service can be provide.

• 한국전자통신학회논문지
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• 제3권2호
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• pp.93-100
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• 2008

본 논문에서는 상업용 MMIC를 이용하여 Ka-대역 위성 텔레비전 방송 수신 전용(TVRO) 저 잡음 하향변환 증폭단을 설계하였다. 저 잡음 블록은 입력단에서 저 잡음 정합시킨 증폭기를 포함한 3단 증폭기, 이미지 제거용 대역통과필터, 주파수 혼합기, 주파수 체배기 및 IF단으로 구성하였다. 저 잡음블럭을 구성하는 모듈에 대한 감쇄와 전력이득에 대한 분석을 통하여 Ka-band LNB의 특성을 만족시키는 소자를 선정하였다. 설계된 저 잡음 블록에 대한 실험 결과 변환이득은 $58{\pm}1dB$, 잡음지수 1.5dB 이하, 위상잡음은 -94.6dBc@10KHz를 나타내었다.

• 전자공학회논문지
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• 제50권10호
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• pp.98-104
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• 2013

본 논문에서는 무선 통신 및 근거리 위치 인식이 가능한 WBAN(wireless body area network) 용 UWB(Ultra-wide band) 수신기 회로를 제안한다. UWB 수신기는 에너지 검출 방식의 OOK(on-off keying) 변조가 가능하도록 설계가 되었다. 고속의 sampling 을 하기 위해서 4bit ADC 는 DLL(delay locked loop) 을 이용하여 sub-sampling 기법을 사용하도록 설계되었다. 제안된 UWB 수신기는 CMOS $0.18{\mu}m$ 공정을 이용하여 설계되었으며, 전원 전압 1.8V에서 61mA의 전류를 소모하면서 -85.7dBm의 수신 감도, 42.1dB의 RF front-end 게인, 3.88 dB의 noise figure, 최대 4m 까지의 거리 감지 성능을 가지고 있다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.265-269
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• 2005

본 논문에서는 5.5GHz 대역 LNA와 1${\times}$2마이크로 스트립 패치 안테나로 구성된 무선랜용 능동안테나를 설계 하였다. LNA는 NEC사의 NE3210S01을 사용하여 잡음 특성을 개선하였으며, 마이크로 스트립 패치안테나는 전방향 특성을 갖도록 설계하였다. 설계된 1${\times}$2마이크로 스트립 패치안테나는 약8.3dBi의 이득을 가지면서 전방향 특성을 나타내었고, LNA는 이득이15dB, 잡음지수는 1dB이하의 특성을 보였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.518-520
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• 2004

In these days, there is a demand to develop fault current limiters(FCLs) to reduce excessive fault current and protect electrical equipments which are installed in the transmission and distribution power systems. We considered the resistive superconducting FCLs among the various kinds of FCLs. In this study, in order to develop the resistive superconducting FCL of 6.6kV 200A $3\phi$, we designed the new mask pattern for etching YBCO films by means of numerical analysis method, current limiting experiments and visualization of bubbles in films and investigated dielectric performance of the designed mask by using elecrtostatic numerical analysis method and breakdown experiments. We etched YBCO films by using the newly designed mask, connected the etched films in series and in parallel, and designed the 6.6kV resistive SFCL and then we observed the current limiting characteristics of the SFCL.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.