• 제목/요약/키워드: Designed in 3D

검색결과 4,309건 처리시간 0.036초

Investigation into Electrical Characteristics of Logic Circuit Consisting of Modularized Monolithic 3D Inverter Unit Cell

  • Lee, Geun Jae;Ahn, Tae Jun;Lim, Sung Kyu;Yu, Yun Seop
    • Journal of information and communication convergence engineering
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    • 제20권2호
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    • pp.137-142
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    • 2022
  • Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

AR based ornament design system for 3D printing

  • Aoki, Hiroshi;Mitanin, Jun;Kanamori, Yoshihiro;Fukui, Yukio
    • Journal of Computational Design and Engineering
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    • 제2권1호
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    • pp.47-54
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    • 2015
  • In recent years, 3D printers have become popular as a means of outputting geometries designed on CAD or 3D graphics systems. However, the complex user interfaces of standard 3D software can make it difficult for ordinary consumers to design their own objects. Furthermore, models designed on 3D graphics software often have geometrical problems that make them impossible to output on a 3D printer. We propose a novel AR (augmented reality) 3D modeling system with an air-spray like interface. We also propose a new data structure (octet voxel) for representing designed models in such a way that the model is guaranteed to be a complete solid. The target shape is based on a regular polyhedron, and the octet voxel representation is suitable for designing geometrical objects having the same symmetries as the base regular polyhedron. Finally, we conducted a user test and confirmed that users can intuitively design their own ornaments in a short time with a simple user interface.

DWA알고리즘을 적용한 Zero-IF 수신기용 2차 3비트 델타-시그마 변조기 (2nd-Order 3-Bit Delta-Sigma Modulator For Zero-IF Receivers using DWA algorithm)

  • 김희준;이승진;최치영;최평
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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    • pp.75-78
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    • 2003
  • In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

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PCS 대역 송신용 CMOS RF/IF 단일 칩 설계 (Design of a CMOS Tx RF/IF Single Chip for PCS Band Applications)

  • 문요섭;권덕기;금거성;박종태;유종근
    • 전기전자학회논문지
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    • 제7권2호
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    • pp.236-244
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    • 2003
  • 본 논문에서는 기존에 값비싼 BiCMOS 공정으로 주로 구현되던 이동통신 단말기용 RF단 및 IF단 회로들을 CMOS 회로로 설계하고, 최종적으로 PCS 대역 송신용 CMOS RF/IF 단일 칩을 설계하였다. 설계된 회로는 IF PLL 주파수합성기, IF Mixer, VGA등을 포함하는 IF 단과, SSB RF Mixer 블록과 구동 증폭기를 포함하는 RF 단으로 구성되며, 디지털 베이스밴드와 전력증폭기 사이에 필요한 모든 신호처리를 수행한다. 설계된 IF PLL 주파수합성기는 100kHz의 옵셋 주파수에서 -114dBc/Hz의 위상잡음 특성을 보이며, lock time은 $300{\mu}s$보다 작고, 3V 전원에서 약 5.3mA의 전류를 소모한다. IF Mixer 블록은 3.6dB의 변환이득과 -11.3dBm의 OIP3 특성을 보이며, 3V 전원에서 약 5.3mA의 전류를 소모한다. VGA는 모든 이득 설정시 3dB 주파수가 250MHz 보다 크며, 약 10mA의 전류를 소모한다. 설계된 RF단 회로는 14.93dB의 이득, 6.97dBm의 OIP3, 35dBc의 image 억압, 31dBc의 carrier 억압 등의 특성을 보이며, 약 63.4mA의 전류를 소모한다. 설계된 회로는 현재 $0.35{\mu}m$ CMOS 공정으로 IC 제작 중에 있다. 전체 칩의 면적은 $1.6㎜{\times}3.5㎜$이고 전류소모는 84mA이다.

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3D 스캐너와 역설계를 활용한 자동차용 허브의 프린팅 특성 (3D Printing Characteristics of Automotive Hub using 3D Scanner and Reverse Engineering)

  • 김해지
    • 한국기계가공학회지
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    • 제18권10호
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    • pp.104-109
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    • 2019
  • Reverse engineering techniques using 3D scanners and 3D printing technologies are being used in various industries. In this paper, the three-dimensional model is designed for automotive hub parts through 3D scanning and reverse engineering, and the design of hub parts is intended to be printed on FDM-style 3D printers to measure and analyze the dimensions of hub parts designed for reverse design and 3D printed hub parts. Experimental result have shown that the dimensions of 3D printed hub parts are small compared to those of the reverse-engineered dimensions, which are due to the shrinkage of filament materials in 3D printing.

Delay 특성을 고려한 광대역 선형 전력 증폭기에 관한 연구 (A Study on Wideband Linear Power Amplifier Considering Delay Characteristics)

  • 김영훈;양승인
    • 한국전자파학회논문지
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    • 제12권1호
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    • pp.37-43
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    • 2001
  • 본 논문에서는 전력증폭기의 선형성을 광대역으로 개선시키기 위하여 delay 특성의영향에 대하여 고려하였다. 사용된 전력 증폭기의 이득은 37dB이고, 3단의 1W급으로 설계되었다. Error 증폭기는 4단으로 설계되었으며 이득은 55dB이다. 그리고 방향성 결합기 및 전력 분배기를 설계하였으며, 또한 크기와 위상을 조절하기 위한 장치로 vector modulator를 사용하였다. 각 모듈을 통합하여 주파수 2.11GHz에서 2.2GHz까지 delay 특성을 고려한 광대역 선형 전력 증폭기를 설계하였으며, 30MHz의 대역폭에 걸쳐 C/I$_3$비가 25dB 이상의 개선 효과를 얻었다.

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7 GHz 대역 100 mW 주파수 3체배기의 제작 (Design of 100mW Frequency Tripler Operating at 7 GHz)

  • 노희정;주재현;구경헌
    • 한국항행학회논문지
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    • 제14권1호
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    • pp.20-26
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    • 2010
  • 본 논문에서는 PHEMT 소자를 이용하여 100mW급 중전력 주파수 3체배기를 설계하였다. 이 주파수 3체배기는 목적하는 주파수 7.2 GHz를 얻기 위하여 2.4 GHz 입력주파수를 정수 체배하여, 3차 고조파를 발생시키는 비선형 소자를 이용하였다. 이 3체배기는 로드-풀 시뮬레이션을 이용하여 설계하였고 출력단에서 기본파와 2차 고조파를 억압하기 위하여 노치필터를 이용하였다. 설계된 3체배기는 출력전력이 21 dBm, 체배 이득이 6 dB이며 기본파는 약 20 dBc, 2차고조파는 약 30 dBc의 고조파억압특성을 나타내었다.

삼차원 재건 기술을 이용한 맞춤형 몽고메리 T-Tube의 제작에 관한 예비 연구 (Custom-Made T-Tube Designed by 3-D Reconstruction Technique, a Preliminary Study)

  • 유영삼
    • 대한기관식도과학회지
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    • 제16권2호
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    • pp.131-137
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    • 2010
  • Background: Montgomery T-tube is widely used to maintain airway in many cases. Market-available tubes are not always fit to the trachea of each patient and need some modification such as trimming. Complications do happen in prolonged use like tracheostomy tubes. To overcome above limitations, we designed custom-made T-tube using CT data with the aid of 3D reconstruction software. Material and Method: Boundaries were extracted from neck CT data of normal person and processed by surface rendering methods. Real laryngotracheal model and tracheal inner surface-mimicking tube model were made with plaster and rubber. The main tube was designed by accumulation of circles or simple closed curves made from boundaries. Stomal tube was made by accumulation of squares due to limitation of software. Measurement data of tracheal lumen were used to custom-made T-tubes. Tracheal lumen residing portion (vertical limb) was made like circular cylinder or simple closed curved cylinder. Stomal portion (horizontal limb) was designed like square cylinder. Results: Custom made T-tube with cylindric vertical limb and horizontal limb of square cylinder was designed. Conclusion: CT data was helpful in making custom made T-tube with 3D reconstruction technique. If suitable materials are available, commercial T-tube can be printed out from 3D printers.

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중전력 주파수 3체배기 설계 및 제작 (Design and Fabrication of the Frequency Tripper for Medium Power)

  • 노희정;이병선
    • 전자공학회논문지 IE
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    • 제47권3호
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    • pp.47-52
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    • 2010
  • 본 논문에서 P-HEMT를 이용한 100 mW급 중전력 주파수체배기를 제안한다. 3차 고조파 성분을 발생 시키는 비선형 장치를 이용하여 2.4GHz의 입력을 3체배 하여 7.2GHz 주파수를 얻도록 설계하였다. 주파수 체배기는 로드풀 모의실험 방식을 이용하여 설게 하였고 기본파와 2차 고조파가 억압된 노치 필터를 사용 하였다. 15dBm 입력에 약21dBm의 출력을 얻도록 하였다 즉 6dB의 변환 이득을 얻었고 기본파에서 20dBc 2차 고조파에서 30dBc의 고조파 억압을 하였다.

Compact LTCC LPF Chip for Microwave Radar Sensor Applications

  • Lee, Young Chul
    • 센서학회지
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    • 제26권6호
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    • pp.386-390
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    • 2017
  • A $5^{th}$-order low-pass filter (LPF) chip implemented in a six-layer low-temperature co-fired ceramic (LTCC) dielectric substrate has been presented. Lumped elements constituting the LPF are designed three-dimensionally in multilayers. In order to improve the parasitic and mutual coupling effects between them, the LPF is designed by sequentially integrating the three-dimensional (3D) lumped elements, by comparing it to the results of the schematic circuit and 3D electromagnetic (EM) analysis. The designed 3D LPF chip was fabricated in a six-layer LTCC substrate as small as $4.0{\times}3.22{\times}0.68mm^3$. The measured return and insertion losses are less than -11 dB and -0.61 dB, respectively, below 1.5 GHz.