• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Journal of Computational Design and Engineering
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• v.2 no.1
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• pp.47-54
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• 2015

In recent years, 3D printers have become popular as a means of outputting geometries designed on CAD or 3D graphics systems. However, the complex user interfaces of standard 3D software can make it difficult for ordinary consumers to design their own objects. Furthermore, models designed on 3D graphics software often have geometrical problems that make them impossible to output on a 3D printer. We propose a novel AR (augmented reality) 3D modeling system with an air-spray like interface. We also propose a new data structure (octet voxel) for representing designed models in such a way that the model is guaranteed to be a complete solid. The target shape is based on a regular polyhedron, and the octet voxel representation is suitable for designing geometrical objects having the same symmetries as the base regular polyhedron. Finally, we conducted a user test and confirmed that users can intuitively design their own ornaments in a short time with a simple user interface.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.10
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• pp.104-109
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• 2019

Reverse engineering techniques using 3D scanners and 3D printing technologies are being used in various industries. In this paper, the three-dimensional model is designed for automotive hub parts through 3D scanning and reverse engineering, and the design of hub parts is intended to be printed on FDM-style 3D printers to measure and analyze the dimensions of hub parts designed for reverse design and 3D printed hub parts. Experimental result have shown that the dimensions of 3D printed hub parts are small compared to those of the reverse-engineered dimensions, which are due to the shrinkage of filament materials in 3D printing.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.37-43
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• 2001

In this paper, we designed a linear power amplifier considering its delay characteristics fur wideband operation. The power amplifier has the gain of 37 dB and is designed in 3-stage typ with 1W output power. The error amplifier has the gain of 55 dB and is designed in 4-stage typ. And directional coupler and power divider are designed. Vector modulator is used to adjust magnitude and phase of signal. A linear power amplifier, that is assembled with each modules, is designed considering the delay characteristics for 2.11~2.2 GHz. Its C/I3 ratio has been improved by B5 dB for bandwidth of 30 MHz.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.20-26
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2 GHz frequency at the output that is an integer multiple of 2.4 GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15 dBm input, i.e., 6 dB conversion gain and the suppression of 20 dBc at fundamental, and 30 dBc at the second harmonics.

• Korean Journal of Bronchoesophagology
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• v.16 no.2
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• pp.131-137
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• 2010

Background: Montgomery T-tube is widely used to maintain airway in many cases. Market-available tubes are not always fit to the trachea of each patient and need some modification such as trimming. Complications do happen in prolonged use like tracheostomy tubes. To overcome above limitations, we designed custom-made T-tube using CT data with the aid of 3D reconstruction software. Material and Method: Boundaries were extracted from neck CT data of normal person and processed by surface rendering methods. Real laryngotracheal model and tracheal inner surface-mimicking tube model were made with plaster and rubber. The main tube was designed by accumulation of circles or simple closed curves made from boundaries. Stomal tube was made by accumulation of squares due to limitation of software. Measurement data of tracheal lumen were used to custom-made T-tubes. Tracheal lumen residing portion (vertical limb) was made like circular cylinder or simple closed curved cylinder. Stomal portion (horizontal limb) was designed like square cylinder. Results: Custom made T-tube with cylindric vertical limb and horizontal limb of square cylinder was designed. Conclusion: CT data was helpful in making custom made T-tube with 3D reconstruction technique. If suitable materials are available, commercial T-tube can be printed out from 3D printers.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.47-52
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• 2010

In this paper, a frequency tripler has been designed with 100mW medium-power using P-HEMT. It is designed to obtain 7.2GHz frequency at the output that is an integer multiple of 2.4GHz input frequency by using nonlinear device that produces 3rd harmonic. The frequency tripler is designed by using load-pull simulation. To suppress the 2nd and fundamental, notch filter is used for the frequency tripler. The tripler is designed to obtain about 21dBm output power with 15dBm input, i.e., 6dB conversion gain and the suppression of 20dBc at fundamental, and 30dBc at the second harmonics.

• Journal of Sensor Science and Technology
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• v.26 no.6
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• pp.386-390
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• 2017

A $5^{th}$-order low-pass filter (LPF) chip implemented in a six-layer low-temperature co-fired ceramic (LTCC) dielectric substrate has been presented. Lumped elements constituting the LPF are designed three-dimensionally in multilayers. In order to improve the parasitic and mutual coupling effects between them, the LPF is designed by sequentially integrating the three-dimensional (3D) lumped elements, by comparing it to the results of the schematic circuit and 3D electromagnetic (EM) analysis. The designed 3D LPF chip was fabricated in a six-layer LTCC substrate as small as $4.0{\times}3.22{\times}0.68mm^3$. The measured return and insertion losses are less than -11 dB and -0.61 dB, respectively, below 1.5 GHz.