• 한국멀티미디어학회논문지
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• 제17권8호
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• pp.1012-1019
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• 2014

The emerging smart utility networks (SUN) provide two-way communications between smart meters and smart appliances for purpose of low power usage, low cost, and high reliability. This paper deals with a bandwidth-efficient communication method based on the hidden pilot-aided scheme using a precoder in downlink SUN suitable for high-rate multimedia applications. With the aid of the design of a precoder and a superimposed hidden pilot, it is possible to estimate the channel without loss of bandwidth. In the channel estimation procedure, the inevitable data interference, which degrades the performance of channel estimation, can be reduced by the precoder design with an iterative scheme. Computer simulations show that the proposed scheme outperforms the conventional method in terms of achievable data rate, especially when a large number of subcarriers are employed.

• 한국CDE학회논문집
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• 제8권1호
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• pp.1-9
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• 2003

Recently, designing 3D objects using various modeling techniques become getting more important issues in related industrial fields. The subdivision scheme is a technique that generates a smooth sur-face through many times of refinement processes that split polygons of control mesh into several smaller polygons. In this paper, we propose a new subdivision algorithm that preserves sharp-edges of control mesh after several refinement processes in the Doo-Sabin subdivision scheme. Using the pro-posed algorithm, the Doo-Sabin subdivision scheme can be well applied to modeling 3D objects with sharp-edges.

• 한국통신학회논문지
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• 제23권5호
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• pp.1282-1290
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• 1998

In this paper, the physical layer design of IMT-2000 system being developed by SK Telecom is introuduced. The outband signaling scheme and the two-pilot scheme are adopted for multimedia service and inter-cell asynchronous mode respectively. In addition, the synchronous transmission scheme is proposed to reduce the interference in the reverse link. The algorithm and simulation results of 'two-pilot scheme' for inter-cell asynchronous mode and 'reverse synchronous control' for synchronous transmission are presented.

• 한국실내디자인학회논문집
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• 제25호
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• pp.191-197
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• 2000

This thesis is focused on the visitors varied experiences of the current museum architecture. The current trend and periodical development of visitors experiences are discussed by analyzing the factors such as the external symbol scheme, the exhibition space scheme, and the visitors circulation scheme which are involved with a visitors experience and thus classifying the experiences related to each sample museum. Examining and providing logical descriptions on each of the schemes helps comprehend the visitors varied experiences. This research, which deals with thoroughly understanding a museum as an architecture followed by taking visitors experiences into account, is aimed to contribute to improving visitors experiences in the course of designing a museum. The above-mentioned types of combination applied to each museum chosen for the research help understand the following : National museums show predominance of specific visitors experiences. As for the external symbol scheme, most of national museums have adopted the temple type, whereas international museums have equally adopted with the temple type and the showroom type which are characterized by its dedication to function and being in balance between contents and formalities.

• 한국콘텐츠학회논문지
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• 제7권8호
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• pp.50-58
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• 2007

본 논문은 대용량 데이터 처리를 위한 실시간 RFID 미들웨어 시스템에서 요구되는 태그 데이터의 필터링 엔진의 동기화를 고려한 필터링 관리기법을 다루고 있다. 응용인터페이스는 HTTP, XML, JMS, SOAP 등의 이는 다양한 프로토콜을 지원하여 다양한 플랫폼에서 본 미들웨어 시스템을 접근하도록 개발되었다. 일반적으로, 필터를 제어하는 클라이언트가 다수가 되는 환경에서 하나의 필터링 화일을 접근하면 동기화 문제가 발생한다. 본 논문에서는 필터 관리프로세스를 통해 동기화를 고려하면서 필터링을 관리하는 기법을 설계하고 구현하였으며, 이를 RFID 미들웨어의 동작 통해 검증한다.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2008년도 학술발표회 논문집
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• pp.1-8
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• 2008

The paper describes the process and issues encountered during the design and construction of seven kilometres of canal to convey 2.5 cumecs of flow to two power stations. The location of the scheme above the primary reservoir of the Waipori Hydropower scheme in Otago, New Zealand, utilising an existing stream diversion into this reservoir, means that no new water abstraction or diversion consents were required. This mini hydro development associated with the existing Waipori scheme was partly justified by an allocation of carbon credits. The scheme controls are slightly more complicated than many canal and penstock schemes as the canal lengths are considerable in relation to the gradient.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.947-950
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• 1999

The PLD design of new scheme LCD driver circuit is described in this paper. A new scheme LCD driver circuit doesn't used microprocessor for the convenience of users. A new scheme LCD driver circuit consists of 4 main parts, that is, a serial/parallel communication control block part, a LCD controller part, a LCD driver part and a RAM/ROM control block part. The validity and efficiency of the proposed LCD driver circuit have been verified by simulation and by ALTERA EPM7192SQC160-15 PLD implementation in VHDL. After comparing this LCD driver circuit to specify it was verified that the developed LCD driver circuit showed has good performances, such as low cost, convenience of users.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.210-213
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• 2002

This paper addresses the design and implementation of compensation of rain attenuation for Ka-band satellite communication system complied with DVB-RCS[2]. A structure of rain fade compensation scheme in the Ka-band satellite communication system is presented. Rain fade compensation scheme in this paper is mainly applied into return-link, which is the path through which user terminal transmit the data tn hub system providing a service. Symbol rate and code rate of channel code are used as variable transmission parameter for rain fade compensation. For estimation of channel environment, SNR of the user terminal which is measured by demodulator of hub system is used. Rain fade compensation scheme in the paper changes the symbol rate and/or code rate according to the measured SNR so that it can compensate the attenuation of the signal.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권11호
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• pp.4331-4346
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• 2015

The femtocell network, which is designed for low power transmission and consists of consumer installed small base stations, coexists with macrocells to exploit spatial reuse gain. For its realization, cross-tier interference mitigation is an important issue. To solve this problem, we propose a joint access and power control scheme that requires limited information exchange between the femto and macro networks. Our objective is to maximize the network throughput while satisfying each user's quality of service (QoS) requirement. To accomplish this, we first introduce two distributed interference detection schemes, i.e., the femto base station and macro user equipment based schemes. Then, the proposed scheme dynamically adjusts the transmission power and makes a decision on the access mode of each femto base station. Through extensive simulations, we show that the proposed scheme outperforms earlier works in terms of the throughput and outage probability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.