• KSII Transactions on Internet and Information Systems (TIIS)
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• 제18권4호
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• pp.1042-1058
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• 2024

Terahertz (THz) communication is becoming a key technology for future 6G wireless networks because of its ultra-wide band. However, the implementation of THz communication systems confronts formidable challenges, notably beam splitting effects and high computational complexity associated with them. Our primary objective is to design a hybrid precoder that minimizes the Euclidean distance from the fully digital precoder. The analog precoding part adopts the delay-phase alternating minimization (DP-AltMin) algorithm, which divides the analog precoder into phase shifters and time delayers. This effectively addresses the beam splitting effects within THz communication by incorporating time delays. The traditional digital precoding solution, however, needs matrix inversion in THz massive multiple-input multiple-output (MIMO) communication systems, resulting in significant computational complexity and complicating the design of the analog precoder. To address this issue, we exploit the characteristics of THz massive MIMO communication systems and construct the digital precoder as a product of scale factors and semi-unitary matrices. We utilize Schatten norm and Hölder's inequality to create semi-unitary matrices after initializing the scale factors depending on the power allocation. Finally, the analog precoder and digital precoder are alternately optimized to obtain the ultimate hybrid precoding scheme. Extensive numerical simulations have demonstrated that our proposed algorithm outperforms existing methods in mitigating the beam splitting issue, improving system performance, and exhibiting lower complexity. Furthermore, our approach exhibits a more favorable alignment with practical application requirements, underlying its practicality and efficiency.

• 한국멀티미디어학회논문지
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• 제9권12호
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• pp.1607-1616
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• 2006

The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1449-1454
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• 2003

For many industrial processes there are good static models used for process design and steady state operation. By using system identification techniques, it is possible to obtain black-box models with reasonable complexity that describe the system well in specific operating conditions [1]. But black-box models using inductive modeling(IM) is not suitable for model based control because they are only valid for specific operating conditions. Thus we need to use deductive modeling(DM) for a wide operating range. Furthermore, deductive modeling is several merits: First, the model is possible to be modularized. Second, we can increase and decrease the model complexity. Finally, we are able to use model for plant design. Power plant must be able to operate well at dramatic load change and consider safety and efficiency. This paper proposes a simplified nonlinear model of an industrial boiler, one of component parts of a power plant, by DM method and applies optimal control to the model.

• Journal of information and communication convergence engineering
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• 제12권4호
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• pp.215-220
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• 2014

We consider quantization optimized for distributed estimation, where a set of sensors at different sites collect measurements on the parameter of interest, quantize them, and transmit the quantized data to a fusion node, which then estimates the parameter. Here, we propose an iterative quantizer design algorithm with a weighted distance rule that allows us to reduce a system-wide metric such as the estimation error by constructing quantization partitions with their optimal weights. We show that the search for the weights, the most expensive computational step in the algorithm, can be conducted in a sequential manner without deviating from convergence, leading to a significant reduction in design complexity. Our experments demonstrate that the proposed algorithm achieves improved performance over traditional quantizer designs. The benefit of the proposed technique is further illustrated by the experiments providing similar estimation performance with much lower complexity as compared to the recently published novel algorithms.

• Journal of Communications and Networks
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• 제5권2호
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• pp.174-183
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• 2003

Space-Time (ST) codes are known to provide high transmission rates, diversity and coding gains. In this paper, a tight upper bound on the error probability of ST codes over rapid fading channels is presented. Moreover, ST codes suitable for rapid fading channels are presented. These codes are designed using the QPSK and 16-QAM signal constellations. The proposed codes are based on two different encoding schemes. The first scheme uses a single trellis encoder, whereas the second scheme uses the I-Q encoding technique. Code design is achieved via partitioning the signal space such that the design criteria are maximized. As a solution for the decoding problem of I-Q ST codes, the paper introduces a low-complexity decoding algorithm. Results show that the I-Q ST codes using the proposed decoding algorithm outperform singleencoder ST codes with equal complexity. The proposed codes are tested over fading channels with different interleaving conditions, where it is shown that the new codes are robust under such imperfect interleaving conditions.

• ETRI Journal
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• 제34권2호
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• pp.284-287
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• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• 한국통신학회논문지
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• 제29권8C호
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• pp.1047-1054
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• 2004

본 논문에서는 AOP(All One Polynomial)에 의해 결정되는 유한체 GF(2$^{m}$ )상의 곱셈을 위한 두 가지 종류의 시스톨릭 어레이를 제안한다. 제안된 두 시스톨릭 어레이 모두 패러럴 입출력 구조를 가진다. 첫 번째 제안된 곱셈기는 O($m^2$)의 면적 복잡도와 O(1)의 시간 복잡도를 가진다. 다시 말하면, 이 곱셈기는 m(m+1)/2 개의 동일한 셀들로 이루어지며 초기 m/2+1 사이클 지연 후, 1 사이클마다 곱셈의 결과를 출력한다. 첫 번째 제안된 곱셈기를 기존의 AOP를 사용하는 병렬형 시스톨릭 곱셈기와 비교 분석한 결과 하드웨어 및 계산지연 시간에 있어 각각 12% 및 50%의 성능 개선을 보인다. 두 번째 제안된 시스톨릭 곱셈기는 암호응용을 위해 선형 어레이로 설계되었으며, O(m)의 면적 복잡도와 O(m)의 시간 복잡도를 가진다. 즉, m+1 개의 동일한 셀들로 이루어지며 m/2+1 사이클마다 곱셈의 결과를 출력한다. 두 번째 곱셈기를 기존의 선형 시스톨릭 곱셈기들과 비교 분석한 결과, 하드웨어, 계산지연 시간, 그리고 처리율에 있어 각각 43%, 83%, 그리고 50%의 성능 개선을 보인다. 또한 제안된 곱셈기들은 높은 규칙성과 모듈성을 가지기 때문에 VLSI 구현에 매우 적합하다. 따라서 GF(2$^{m}$ ) 응용을 위해, 본 연구에서 제안된 곱셈기들을 사용하면 최소의 하드웨어 사용으로 최대의 성능을 얻을 수 있다.

• 전자공학회논문지
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• 제49권12호
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• pp.201-208
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• 2012

본 논문에서는 실시간 동영상 부호화를 위한 효과적인 비트율 제어 방법을 제안하고 하드웨어로 구현한다. 제안하는 비트율 제어는 각 기본유닛 마다 R-D 파라미터 갱신에 의해 많은 연산 처리를 필요로 하는 이차원 R-D 모델을 사용하지 않고, 프레임의 평균 복잡도 가중치를 이용한 Qstep 결정 모델을 사용함으로써 연산량을 감소시킨다. 또한 적은 연산량과 빠른 MAD 예측을 위해 부호화된 기본유닛을 기반으로 영상의 공간적 및 시간적 상관관계를 이용하여 MAD를 예측한다. 제안하는 비트율 제어는 프레임 레벨 MAD 예측과 매크로블록 레벨 MAD 예측, GOP 비트 할당, 프레임 비트 할당, 가상버퍼, Qstep 결정 모델, 비트율 제어 파라미터 갱신, QP 결정 모듈을 포함하며 총 8개의 모듈로 구성된다. 비트율 제어 하드웨어는 Verilog-HDL을 이용하여 설계하였으며, Synopsys사의 Design Compiler를 이용하여 UMC 공정 $0.18{\mu}m$ 셀 라이브러리로 합성한 결과, 최대 동작 주파수는 108 MHz이고, 게이트 수는 19.1k이다. 실험 결과로부터 제안한 구조는 기존 구조 보다 게이트 수가 85% 감소하였고, 매크로블럭 당 QP를 결정하는데 평균 220 사이클 수가 소요되어 기존 구조보다 64% 단축됨을 확인하였다.