• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.395-398
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• 2004

This paper describes the implementation of an internet-based servo-control system with novel direct internet control architecture which is insensitive to the inherent internet time delay. The servo control system can be controlled by using a PC provided at a local site. However, a large internet time delay may make some control inputs distorted. Moreover, since it is acted by the number of the internet nodes and loads, this delay is variable and unpredictable. This system consists of servo mechanism and Ethernet control adapter. Intention of this paper is to reduce the expenses, to manage effectively for plant and to increase the productivity through linking each plant of several factories by TCP/IP and Ethernet, and then many control plants and manager minimize the needed work. Experiments are partially fulfilled using the Labview and Matlab.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.3-9
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• 2015

The wireless communication system adopts an appropriate retransmission scheme on each system protocol layer to improve reliability of data transmission. In each system protocol layer, the retransmission scheme operates in independently other layers and operates based on the parameters without reference to end-to-end performance of wireless communication system. For this reason, it is difficult to design the optimal system parameters that satisfy the QoS requirements for each service class. Thus, the performance analysis of wireless communication system is needed to design the optimal system parameters according to the end-to-end QoS requirements for each service class. In this paper, we derive the mathematical model to formulate the end-to-end performance of wireless communication system. We also evaluate the performance at the MAC and transport layers in terms of average spectral efficiency and average transmission delay. Based on the results of performance evaluations, we design the optimal system parameters according to the QoS requirements of service classes. From the results, the HARQ combined with AMC is appropriate for the delay-sensitive service and the ARQ combined with AMC is appropriate for a service that is insensitive to transmission delay. Also, the TCP can be applied for the delay-insensitive service only.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2C
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• pp.181-192
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• 2003

Blind equalization of communication channel is important because it does not need training signal, nor does it require a priori channel information. So, we can increase the bandwidth efficiency. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind channel equalizer length mismatch as well as for its simple adaptive implementation. Unfortunately, the previous one-step prediction error method is known to be limited in arbitrary decision delay. In this paper, we propose method for fractionally spaced blind equalizer with arbitrary decision delay using one-step forward prediction error filter from second-order statistics of the received signals for SIMO channel. Our algorithm utilizes the forward prediction error as training signal and computes the best decision delay from all possible decision delay. Simulation results are presented to demonstrate the performance of our proposed algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.3
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• pp.289-295
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• 1998

The purpose of this paper is to propose an improvement method of BER for coded 16-QAM under Rayleigh fading channel. To overcome the BER degradation due to the fading under mobile communication, we apply delay modulation technique which is efficient to get both a coding gain and approximately one-half those needed by Manchester coding on bandwidth requirements. Especially, the delay modulation scheme is insensitive to the $180^{\circ}$phase ambiquity common to NRZ-L and Manchester coding schemes. From the computer simulation, BER performance of our scheme has achieved about 3.8 dB improvement of about $10^{-4}$, compared to Manchester coded 16-QAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11B
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• pp.953-959
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• 2006

This paper provides optimum TCP/IP packet size that maximizes the throughput efficiency of ATM layer as a function of TCP/IP packet length for several values of channel BER over wireless ATM LAN links applying data link error control schemes to reduce error problems encountered in using wireless links. For TCP/IP delay-insensitive traffc requiring reliable delivery, it is necessary to adopt data link layer ARQ protocol. So ARQ error control schemes considered in this paper include GBN ARQ, SR ARQ and type-I Hybrid ARQ, which ARQ is needed, but FEC can be used to reduce the number of retransmissions. Especially adaptive type-I Hybrid ARQ scheme is necessary for a variable channel condition to make the physical layer as SONET-like as possible.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.869-872
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• 2001

Blind identification and equalization of communication channel is important because it does not need training sequence, nor does it require a priori channel information. So, we can increase the bandwidth efficiency. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind channel estimator and equalizer length mismatch as well as for its simple adaptive algorithms. In this paper, we propose method for fractionally spaced blind equalizer with arbitrary delay using one-step forward prediction error filter from second-order statistics of the received signals for SIMO channel. Our algorithm utilizes the forward prediction error as training sequences for data estimation and desired signal for channel estimation.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.5
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• pp.42-53
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• 2016

This study aims to evaluate the performance of Hook-turn operation with various sizes of bicycle waiting zone(WZ) and to determine the optimal size of bicycle WZ under various traffic and control circumstances. An extensive simulation study was performed to examine bicycle and vehicle delay trends for given experimental design. Results showed that vehicle delay was insensitive to the size of waiting zone, but bicycle delay was reduced as the size of waiting zone increased in general. The delay performance indicated a similar trend between with RTOR and without RTOR operation, but vehicle delay slightly increased and bicycle delay slightly decreased without RTOR. Regarding to optimal waiting zone size, 6 WZ was recommended for general conditions with RTOR, but 9 WZ was recommended when bicycle left-turn volume was greater than 120 v/h. 6 WZ was recommended for general conditions without RTOR, but 12 WZ was recommended when bicycle left-turn volume was greater than 90 v/h.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.