• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.209-219
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• 1995

As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.104-112
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• 2007

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.131-147
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• 2024

A routing strategy based on traffic prediction and dynamic cache allocation for satellite nodes is proposed to address the issues of high propagation delay and overall delay of inter-satellite and satellite-to-ground links in low Earth orbit (LEO) satellite systems. The spatial and temporal correlations of satellite network traffic were analyzed, and the relevant traffic through the target satellite was extracted as raw input for traffic prediction. An improved gradient boosting regression tree algorithm was used for traffic prediction. Based on the traffic prediction results, a dynamic cache allocation routing strategy is proposed. The satellite nodes periodically monitor the traffic load on inter-satellite links (ISLs) and dynamically allocate cache resources for each ISL with neighboring nodes. Simulation results demonstrate that the proposed routing strategy effectively reduces packet loss rate and average end-to-end delay and improves the distribution of services across the entire network.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.6-15
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• 2000

In this paper, we propose a high speed parallel multiplier with a hierarchical architecture using a fast 4-2 compressor and 6-2 compressor. Generally, the performance of parallel multiplier depends on the processing speed of partial products summation tree with CSA adder. In this paper we propose a new circuit of 4-2 compressor and 6-2 compressor which reduces the propagation delay time, compared with conventional one. We Propose a hierarchical multiplier architecture in order to improve the execution speed of 16$\times$16 parallel multiplier using proposed compressors in this paper and make layout design easily by regular structure. The propagation delay time of the proposed 4-2 compressor circuit was 14% reduced as a result of SPICE simulation, compared with the conventional 4-2 compressor. The total propagation delay time of proposed 16$\times$16 parallel multiplier was 12% reduced using proposed 4-2 compressor and 6-2 compressor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.104-113
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• 2000

In this paper, we propose a protocol that makes use of a concept of a meta-group based on propagation trees to deal with duplicated members of the same multicast group. It is shown that, if multicast tree is composed ofthese meta-groups, the depth of the tree can be shortened and the ordering of the multicast that communicatesbetween multiple senders and receivers can be easier. In the protocol, we assign a Designated Manager(DM) toeach meta-group and make each DM do the role of the representative receiver of the meta group. In this Paper,the DM's are supposed to handle ACK and retransmission for the members in the same meta group. Hence, theDM's distribute the ACK from senders, and they can reduce the burden of senders by shortening commit delaytime. We also show, through a simulation analysis, that the new multicast protocol outperforms the existing onesnot only in message costs but also in commit delay times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• The KIPS Transactions:PartD
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• v.10D no.4
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• pp.647-654
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• 2003

The replication of data is used to increase its availability and to improve the performance of a system. The distributed database system has to maintain both the database consistency and the replica consistency. This paper proposes an algorithm which resolves the conflict of the operations by using the mechanism based on the structure that the replicas of each data item are hierarchically organized. Each update is propagated along the tree based on the fact that the root of each data item is the primary replica in partially replicated databases. The use of a hierarchy of data may eliminate useless propagation since the propagation can be done only to sites having the replicas. In consequence, the propagation delay of updates may be reduced. By using the timestamp and a compensating transaction, our algorithm resolves the non-serializability problem caused by the conflict of operations that can happen on the way of the update propagation due to the lazy propagation. This resolution also guarantees the data consistency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9A
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• pp.874-881
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• 2010

Acoustic signal, which is a main carrier of underwater communication, attenuates along the traveled path heavily depending on the frequency as well as inter-node distance. In addition, since it has a long propagation delay, the conventional medium access control (MAC) schemes requiring complex signaling procedures and accordingly heavy overhead messages would not be appropriate in underwater communications. In this paper, we propose a code division multiple access (CDMA) scheme as a solution for MAC of underwater communication and evaluate the performance. A hierarchical data-gathering tree topology is considered and a staggered wake-up pattern is employed for the purpose of energy saving. As a performance measure, the data rate at each level of hierarchical topology is derived.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.12
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• pp.1328-1336
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• 2012

Compared to terrestrial RF communications, underwater acoustic communications have several limitations such as limited bandwidth, high level of fading effects, and a large underwater propagation delay. In this paper, in order to tackle those limitations of underwater communications and to make it possible to form a large underwater monitoring systems, we propose a hierarchical underwater network architecture, which consists of underwater sensors, clusterheads, underwater/surface sink nodes, autonomous underwater vehicles (AUVs). In the proposed architecture, for the maximization of packet delivery ratio and the minimization of underwater sensor's energy consumption, a hybrid routing protocol is used. More specifically, cluster members use Tree based routing to transmit sensing data to clusterheads. AUVs on optimal trajectory movements collect the aggregated data from clusterhead and finally forward the data to the sink node. Also, in order to minimize the maximum travel distance of AUVs, an Integer Linear Programming based algorithm is employed. Performance analysis through simulations shows that the proposed architecture can achieve a higher data delivery ratio and lower energy consumption than existing routing schemes such as gradient based routing and geographical forwarding. Start after striking space key 2 times.

• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.200-203
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• 2012

Epoxy/mica composite was synthesized, in order to use it as an impregnation resin in a vacuum pressure impregnation (VPI) process, for manufacturing a high voltage rotary machine. The average particle size of the mica was 5~7 ${\mu}m$ and its content was 0, 20, 30 and 40 wt%. A plasticizer or a low molecular aliphatic epoxy was also used, to decrease the viscosity of the composite. The AC electrical breakdown strength was estimated in sphere-to-sphere electrodes, and the electrical breakdown data were estimated by Weibull statistical analysis. The electrical breakdown strength became higher with the addition of mica; and that of the system with 20 wt% mica was highest. The electrical breakdown strength of the system with an aliphatic epoxy was higher than that of the system with a, plasticizer.