• 동력기계공학회지
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• 제10권4호
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• pp.159-164
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• 2006

In recent, the marine engine of a large size is being realized a lower speed, longer stroke and a small number of cylinders for the energy saving. Consequently the variation of rotational torque became larger than former days because of the longer delay-time in fuel oil injection process and an increased output per cylinder. It was necessary that algorithms have enough robustness to suppress the variation of the delay-time and the parameter perturbation. This paper shows the structure of hybrid F-NFC against the delay-time and the perturbation of engine parameter as modeling uncertainties, and the design of the robust speed controller by hybrid F-NFC for the engine. And, The Parameter values of linear equation are determined by RC-GA for F-NFS. The hybrid F-NFC is combined the F-NFC and PID controller for filling up each.

• Journal of Power Electronics
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• 제11권2호
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• ETRI Journal
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• 제24권5호
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• pp.360-372
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• 2002

In this paper, we propose the modified dynamic weighted round robin (MDWRR) cell scheduling algorithm, which guarantees the delay property of real-time traffic and also efficiently transmits non-real-time traffic. The proposed scheduling algorithm is a variation of the dynamic weighted round robin (DWRR) algorithm and guarantees the delay property of real-time traffic by adding a cell transmission procedure based on delay priority. It also uses a threshold to prevent the cell loss of non-real-time traffic that is due to the cell transmission procedure based on delay priority. Though the MDWRR scheduling algorithm may be more complex than the conventional DWRR scheme, considering delay priority minimizes cell delay and decreases the required size of the temporary buffer. The results of our performance study show that the proposed scheduling algorithm has better performance than the conventional DWRR scheme because of the delay guarantee of real-time traffic.

• 전자공학회논문지B
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• 제28B권11호
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• 한국자동차공학회논문집
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• 제2권6호
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• pp.76-86
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• 1994

Combustion of diesel engine depends on the mixing of air and evaporating fuel during ignition delay greatly. Variation of air-fuel mixing rate and ignition delay for engine operating condition causes difference of combustion, performance and exhaust emissions. This study is investigated in a turbocharged diesel engine of IDI swirl chamber type. In the results, As injection timing is advanced until $12.6^{\circ}$ BTC, ignition delay decreases. NOx concentration and smoke level in exhaust gas increases for advanced injection timing Ignition delay, combustion period, pressure rise rate and exhaust gas temperature are increased with increasing engine speed. And ignition delay at high load is more decreased than that at low load. Ignition delay and combustion period are decreased with increasing intake pressure. Power increases, temperature and CO, NOx concentration in exhaust gas decreases as intake pressure increases. With increasing load, ignition delay is decreased and combustion period, motoring pressure are increased.

• 한국컴퓨터정보학회논문지
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• 제20권9호
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.

• 한국통신학회논문지
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• 제28권4B호
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• pp.270-281
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• 2003

E-PON 은 광대역 액세스 망에서 급증하는 인터넷 데이터 트래픽을 지원하고 대역폭의 동적 할당 기능을 효과적으로 지원한다. 본 논문에서는 E-PON에서 QoS를 고려한 트래픽과 최선형(Best-Effort) 트래픽의 두 가지 형식을 가진 트래픽이 유입될 때 QoS 서비스에 제약된 지연 시간과 지연 변이를 보장하고 최선형 서비스에는 대역폭을 최대학 보장해 주는 Dual-GPS 스케쥴러를 제안한다. 제안된 기법은 Ethernet 수동형 광 네트워크에서 상향 데이터 전송 시 새로운 슬롯할당 기법을 통하여 QoS 가 요구되는 전송 플로우에 대해 제약된 지연시간과 지연 변이를 제어하는 특성을 보인다. 시뮬레이션 결과 제안하는 기법이 기존의 대역할당 기법보다 지연 및 지연 변이 제어능력이 우수하다.

• 한국GIS학회:학술대회논문집
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• 한국GIS학회 2004년도 GIS/RS 공동 춘계학술대회 논문집
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• pp.235-240
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• 2004

Time Delay and Integration (TDI) 기법을 사용하는 고해상도 위성 영상기에 있어서 실제 위성 운영시 발생하는 위성 고도의 순간적 변화에 대한 TDI 일치를 연구하였다. 시간에 따라 변하는 순간 고도의 특성을 분석하였고 순간 고도 변화가 TDI 불일치를 초래하여 위성 영상 기기의 성능에 미치는 영향을 분석하였다. TDI 시간 지연을 조절하여 실제 위성 운영에서 순간적으로 발생하는 TDI 불일치를 보정하고 성능을 향상시킬 수 있는 가능성을 연구하였다. 본 연구 결과는 위성 영상 품질 향상에 활용될 수 있다.

• 한국산학기술학회논문지
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• 제13권11호
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• pp.5512-5517
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• 2012

본 논문에서는 만족스런 서비스 품질을 제공하는 페트리 네트 기반의 멀티미디어 동기화 모델을 제안한다. 제안한 모델은 실시간 특징을 나타내는 데이터의 서비스 품질을 보장할 수 있는 가변적 버퍼를 적용하였다. 본 논문은 동기화 구간 조정을 처리하기 위해 지연 지터를 적용함으로써 트래픽 증가로 인한 미디어 데이터의 손실 시간 및 지연시간의 변화로 인한 데이터 손실을 감소시켰다. 그리고 스무딩 버퍼의 대기 시간을 가변으로 처리함으로써 지연시간의 변화로 인한 불연속을 감소시켰다. 제안된 논문은 고품질 서비스의 보장을 요구하는 시스템에 적합하며, 재생율 증가와 손실율 감소 등 서비스 품질을 향상시켰다.

• 대한전자공학회논문지TC
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• 제38권10호
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• pp.24-33
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• 2001

패킷 통신에 있어서 주요 서비스 품질(QoS : Quality of Service) 요소로는 지연(delay), 지연 변이(delay variation), 패킷 손실율(loss rate) 등이 있다. 본 논문에서는 복수의 논리적 버퍼가 하나의 메모리 버퍼를 공유할 때, 논리버퍼의 손실율 성능을 향상시키기 위한 새로운 버퍼 할당 기법을 제안한다. 제안된 예방적 적응 한계치(PAT : Preventive Adaption Threshold) 버퍼 할당 기법은 기존의 동적 한계치 (Dynamic Threshold)기법에서 사용하는 패킷 폐기 한계치(threshold)의 직선적 변화 궤적과는 다른 한계치 동적 변화 궤적을 사용함으로써 패킷 손실율 성능을 개선하였다. 제안된 기법의 성능을 평가하기 위하여 기존의 무제어(NC : No Control), 고정 한계치(ST : Static Threshold), 동적 한계치(DT : Dynamic Threshold)등의 기법과 여러 측면에서 손실율 성능을 비교하였다.