• Journal of Power System Engineering
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• v.10 no.4
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• pp.159-164
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• 2006

In recent, the marine engine of a large size is being realized a lower speed, longer stroke and a small number of cylinders for the energy saving. Consequently the variation of rotational torque became larger than former days because of the longer delay-time in fuel oil injection process and an increased output per cylinder. It was necessary that algorithms have enough robustness to suppress the variation of the delay-time and the parameter perturbation. This paper shows the structure of hybrid F-NFC against the delay-time and the perturbation of engine parameter as modeling uncertainties, and the design of the robust speed controller by hybrid F-NFC for the engine. And, The Parameter values of linear equation are determined by RC-GA for F-NFS. The hybrid F-NFC is combined the F-NFC and PID controller for filling up each.

• Journal of Power Electronics
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• v.11 no.2
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• ETRI Journal
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• v.24 no.5
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• pp.360-372
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• 2002

In this paper, we propose the modified dynamic weighted round robin (MDWRR) cell scheduling algorithm, which guarantees the delay property of real-time traffic and also efficiently transmits non-real-time traffic. The proposed scheduling algorithm is a variation of the dynamic weighted round robin (DWRR) algorithm and guarantees the delay property of real-time traffic by adding a cell transmission procedure based on delay priority. It also uses a threshold to prevent the cell loss of non-real-time traffic that is due to the cell transmission procedure based on delay priority. Though the MDWRR scheduling algorithm may be more complex than the conventional DWRR scheme, considering delay priority minimizes cell delay and decreases the required size of the temporary buffer. The results of our performance study show that the proposed scheduling algorithm has better performance than the conventional DWRR scheme because of the delay guarantee of real-time traffic.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.6
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• pp.76-86
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• 1994

Combustion of diesel engine depends on the mixing of air and evaporating fuel during ignition delay greatly. Variation of air-fuel mixing rate and ignition delay for engine operating condition causes difference of combustion, performance and exhaust emissions. This study is investigated in a turbocharged diesel engine of IDI swirl chamber type. In the results, As injection timing is advanced until $12.6^{\circ}$ BTC, ignition delay decreases. NOx concentration and smoke level in exhaust gas increases for advanced injection timing Ignition delay, combustion period, pressure rise rate and exhaust gas temperature are increased with increasing engine speed. And ignition delay at high load is more decreased than that at low load. Ignition delay and combustion period are decreased with increasing intake pressure. Power increases, temperature and CO, NOx concentration in exhaust gas decreases as intake pressure increases. With increasing load, ignition delay is decreased and combustion period, motoring pressure are increased.

• Journal of the Korea Society of Computer and Information
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• v.20 no.9
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.270-281
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• 2003

E-PON supports efficiently the increased Internet data traffic and efficient bandwidth assignment function by which the shared upstream bandwidth in the broadband access networks. In this paper, when different types of incoming sources are mapped into QoS-aware source and Best-Effort(BE) source, we propose the Dual-GPS schedulaer in E-PON that has the characteristics to provide delay and delay-constraint application, and maximizes the bandwidth to best-effort service. When transmit upstream data in E-PON, The proposed scheme supports the control capabilities of delay and delay-variation for required QoS flow through the novel bandwidth assignment scheme. Simulation results show our scheme outperforms the conventional bandwidth allocation scheme in controlling the delay and delay-variation of E-PON system.

• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2004.03a
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• pp.235-240
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• 2004

Time Delay and Integration (TDI) 기법을 사용하는 고해상도 위성 영상기에 있어서 실제 위성 운영시 발생하는 위성 고도의 순간적 변화에 대한 TDI 일치를 연구하였다. 시간에 따라 변하는 순간 고도의 특성을 분석하였고 순간 고도 변화가 TDI 불일치를 초래하여 위성 영상 기기의 성능에 미치는 영향을 분석하였다. TDI 시간 지연을 조절하여 실제 위성 운영에서 순간적으로 발생하는 TDI 불일치를 보정하고 성능을 향상시킬 수 있는 가능성을 연구하였다. 본 연구 결과는 위성 영상 품질 향상에 활용될 수 있다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5512-5517
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• 2012

In this paper we suggest multimedia synchronization model that is based on the Petri-net and services desirable quality of service requirement. Proposed model applies variable buffer which can be allowed, and then it presents high quality of service and real time characteristics. This paper decreases the data loss resulted from variation of delay time and from loss time of media-data by means of applying delay jitter in order to deal with synchronization interval adjustment. Plus, the mechanism adaptively manages the waiting time of smoothing buffer, which leads to minimize the gap from the variation of delay time. The proposed paper is suitable to the system which requires the guarantee of high quality of service and mechanism improves quality of services such as decrease of loss rate, increase of playout rate.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.24-33
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• 2001

Delay, delay variation and packet loss rate are principal QoS(Quality of Service) elements of packet communication. This paper proposes a new buffer allocation mechanism to improve the packet loss performance in such a situation that multiple logical buffers share a single physical memory buffer. In the proposed buffer allocation mechanism, the movement of dynamic threshold follows a curved track instead of a straight line which is used in the DT(dynamic threshold) mechanism. In order evaluate the effectiveness of the proposed mechanism, it is compared with the existing previously proposed mechanisms in several aspects including NC(no control), ST(Static Threshold) and DT mechanisms.