• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.354-358
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• 2001

Cosim (Hardware and Software Co-Simulator) is a JavaBeans-based simulation tool fur validating systems architecture and estimating performance of web applications. Cosim has four components: Modeler, Translator, Engine and Scenario. Users start from Modeler to describe systems architecture in UML(Unified Modeling Language) deployment diagram, and then specify hardware & software performance parameters such as execution delay, network topology, and frame size. All information specified on Modeler are sent to Translator, and then automatically converted to Java programs. Scenario is responsible to run the Java program and produce results in text reports and graphs. Developers can reduce development time and cost by validating systems architecture of web applications before the actual deployment.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.115-124
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• 1994

In this paper, we have developed a performance analysis tool for communication networks called COMNAS. COMNAS analyses the performance of wide area networks such as Korea Educational Network and Korea Research Environment Open Network which include local area networks such as Ethernet and Token Ring. COMNAS consists of model constructor, simulation implementor, output analyzer and user interface. Attributes of communication networks for modeling either have default values or are entered by user as object units, and implementation of simulation is automatically proceeded by user interface. Ouput results obtained by COMNAS are the status of node, link and entire network such as mean message transmission delay, throughput, utilization, and so on, and they can be selectively obtained upon the request of the user.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Journal of Korean Institute of Industrial Engineers
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• v.34 no.3
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• pp.296-307
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• 2008

A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1996.10a
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• pp.96-100
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• 1996

So far the analysis and modeling of cutting process is studied commonly assumed as being linear stochastic or chaotic without experimental verification. So we verified force signals of cutting process(ball end-milling) is low-dimensional chaos by calculating Lyapunov Exponents. reconstructing attractor using time delay coordinates and calcula-ting it's fractal dimension.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.183-187
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• 2003

The expression for the effects of an amplitude imbalance, a phase imbalance and a delay mismatch on the characteristics of a linearization loop in feedforward amplifiers is derived and analyzed. The simulation results are compared with the results obtained by means of using a commercial simulation tool and the exact agreement is reported.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.176-181
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• 2000

Collision free task planning for dual-arm robot which perform many subtasks in a common work space can be achieved in two steps : path planning and trajectory planning. path planning finds the order of tasks for each robot to minimize path lengths as well as to avoid collision with static obstacles. A trajectory planning strategy is to let each robot move along its path as fast as possible and delay one robot at its initial position or reduce speed at the middle of its path to avoid collision with the other robot.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2167-2170
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• 2002

In this paper, model-based tuning rules of the PID controller are proposed incorporating with genetic algorithms. Three sets of optimal PID parameters for set-point tracking are obtained based on the first-order time delay model and a genetic algorithm as a optimization tool which minimizes performance indices(IAE, ISE and ITAE). Then tuning rules are derived using the tuned parameter sets, potential rule models and a genetic algorithm. Simulation is carried out to verify the effectiveness of the proposed rules.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.509-512
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• 2003

The Critical Path Method(CPM) is an effective tool used for planning and scheduling. One of strong point in the CPM is what can calculate float. Float is able to prolong without having an effect on overall schedule of project, however concept and scope about ownership is not definite, because it is a by-product of project. Thus participants have had many dispute in using float because of their interests. In recent years, a few theories have evolved in an attempt to solve this problem. But the prior research did not make a reasonable distribution of float because their criteria of distribution was based on ratio for total project time. Actually, an application of float is achieved by participant's delay risk. Therefore. this paper proposes criteria for float distribution using delay risks, and the framework for the assessment of the delay risks.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.261-272
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• 2003

An Ethernet PON(Passive Optical Network) is an economical and efficient access network that has received significant research attention in recent years. A MAC(Media Access Control) protocol of PON , the next generation access network, is based on TDMA(Time Division Multiple Access) basically and can classify this protocol into a fixed length slot assignment method suitable for leased line supporting QoS(Quality of Service) and a variable length slot assignment method suitable for LAN/MAN with the best effort. For analyzing the performance of these protocols, we design an Ethernet PON model using OPNET tool. To establish the maximum efficiency of a network, we verify a MAC protocol and determine the optimal number of ONUs(Optical Network Unit) that can be accepted by one OLT(Optical Line Terminal) and propose the suitable buffer size of ONU based on analyzing the end-to-end Ethernet delay, queuing delay, throughput, and utilization.