• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2001년도 The Seoul International Simulation Conference
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• pp.354-358
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• 2001

Cosim (Hardware and Software Co-Simulator) is a JavaBeans-based simulation tool fur validating systems architecture and estimating performance of web applications. Cosim has four components: Modeler, Translator, Engine and Scenario. Users start from Modeler to describe systems architecture in UML(Unified Modeling Language) deployment diagram, and then specify hardware & software performance parameters such as execution delay, network topology, and frame size. All information specified on Modeler are sent to Translator, and then automatically converted to Java programs. Scenario is responsible to run the Java program and produce results in text reports and graphs. Developers can reduce development time and cost by validating systems architecture of web applications before the actual deployment.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.115-124
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• 1994

In this paper, we have developed a performance analysis tool for communication networks called COMNAS. COMNAS analyses the performance of wide area networks such as Korea Educational Network and Korea Research Environment Open Network which include local area networks such as Ethernet and Token Ring. COMNAS consists of model constructor, simulation implementor, output analyzer and user interface. Attributes of communication networks for modeling either have default values or are entered by user as object units, and implementation of simulation is automatically proceeded by user interface. Ouput results obtained by COMNAS are the status of node, link and entire network such as mean message transmission delay, throughput, utilization, and so on, and they can be selectively obtained upon the request of the user.

• 전자공학회논문지A
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• 제32A권10호
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• 대한산업공학회지
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• 제34권3호
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• pp.296-307
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• 2008

A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1996년도 추계학술대회 논문
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• pp.96-100
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• 1996

So far the analysis and modeling of cutting process is studied commonly assumed as being linear stochastic or chaotic without experimental verification. So we verified force signals of cutting process(ball end-milling) is low-dimensional chaos by calculating Lyapunov Exponents. reconstructing attractor using time delay coordinates and calcula-ting it's fractal dimension.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.183-187
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• 2003

The expression for the effects of an amplitude imbalance, a phase imbalance and a delay mismatch on the characteristics of a linearization loop in feedforward amplifiers is derived and analyzed. The simulation results are compared with the results obtained by means of using a commercial simulation tool and the exact agreement is reported.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2000년도 춘계학술대회논문집 - 한국공작기계학회
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• pp.176-181
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• 2000

Collision free task planning for dual-arm robot which perform many subtasks in a common work space can be achieved in two steps : path planning and trajectory planning. path planning finds the order of tasks for each robot to minimize path lengths as well as to avoid collision with static obstacles. A trajectory planning strategy is to let each robot move along its path as fast as possible and delay one robot at its initial position or reduce speed at the middle of its path to avoid collision with the other robot.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2167-2170
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• 2002

In this paper, model-based tuning rules of the PID controller are proposed incorporating with genetic algorithms. Three sets of optimal PID parameters for set-point tracking are obtained based on the first-order time delay model and a genetic algorithm as a optimization tool which minimizes performance indices(IAE, ISE and ITAE). Then tuning rules are derived using the tuned parameter sets, potential rule models and a genetic algorithm. Simulation is carried out to verify the effectiveness of the proposed rules.

• 한국건설관리학회:학술대회논문집
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• 한국건설관리학회 2003년도 학술대회지
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• pp.509-512
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• 2003

Critical Path Mettled(CPM)은 공정을 계획하고 관리하는데 효과적인 도구이다. CPM의 장점 중 한 가기는 여유시간(Float)을 계산할 수 있다는 것이다. 여유시간은 프로젝트 전체의 공기에 영향을 주기 않고 연장할 수 있지만 공정관리 상의 부산물이기 때문에 소유권에 대한 개념과 범위가 명확하지가 않다. 때문에 사업참여자들이 여유시간을 사용할 때에는 이해관계가 얽혀있어 많은 분쟁을 일으켰다. 이를 해결하기 위해 여유시간 분배와 소유권에 대한 연구가 진행되어 왔으나 여유시간 분배의 기준을 전체 공정에 대한 비율에 두고 있어 합리적인 분배가 이루어지기 못했다. 따라서 본 연구에서는 여유시간 활용목적에 대해 분석한 결과를 기반으로 하여 여유시간 분배 기준을 공기지연 리스크로 제시하였고, 소유권의 개념을 적용시키기 위해 사업참여자 주체별로 공기지연 리스크인자를 구분하였다. 또한 공기지연 리스크인자가 전체 공정에 대해 일률적으로 영향을 끼치는 것이 아니기 때문에 공종에 따라 공기지연 리스크인자들의 영향력을 평가하기 위한 Framework을 구축하였고, 평가를 위한 방법과 기준을 활용할 수 있는 분배방법을 제시하였다.

• 대한전자공학회논문지TC
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• 제40권7호
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• pp.261-272
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• 2003

Ethernet PON(Passive Optical Network)은 최근 활발하게 연구되고 있는 경제적이고 효율적인 가입자망이다. 차세대 가입자망인 Ethernet PON의 MAC(Media Access Control) 프로토콜은 TDMA(Time Division Multiple Access)방식을 기본으로 하며, QoS(Qualify of Service)를 보장해야 하는 전용회선(Leased Line) 가입자에 적합한 고정 할당 방식과 LAN/MAN의 최선형(Best Effort) 방식에 적합한 동적 할당 방식으로 나눌 수 있다. 본 논문에서는 이들 프로토콜의 성능을 분석하기 위하여 OPNET 시뮬레이션 도구를 이용해 Ethernet PON 모델을 설계한다. 설계된 모델에 대한 단대단 Ethernet 지연(end-to-end Ethernet delay), 큐잉 지연(queuing delay), 처리(throughput)과 사용률(utilization) 분석을 통해서 MAC 프로토콜을 검증하고, 하나의 OLT(Optical Line Terminal)가 수용할 수 있는 최적의 ONU(Optical Network Unit) 개수를 산정한다. 또한, 적정한 ONU의 버퍼 크기를 제안하여 Ethernet PON의 망 효율을 극대화하는 방안을 제시한다.