• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2007.11a
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• pp.68-74
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• 2007

Critical Chain Project Management(CCPM) is a new project management system paradigm which maintains the advantages of PERT/CPM and improves the shortcomings of it. In CCPM the task durations are determined as 50% time estimates, ie average time discarding the their contingency. CCPM determines the critical chain the constraint of a projects considering the logical precedence relationship and resource conflict resolution. Project buffer is located at the end of critical chain to absorb the variations of critical chain. The size of project buffer is usually calculated as the half of the sum of critical chain length. Also feeding buffer is inserted after each non-critical chain which feeding into the critical chain to prevent the time delay of critical chain from uncertainties of non-critical chains. Resource buffer can be utilized to improve the availability of resources of critical chain. Buffer management is a project execution and control mechanism. Buffers are classified into 3 zones. They are OK zone, Watch and Plan zone and Expediting zone. If the project status is within Watch and Plan zone, contingency plan is established. And if it changes into Expediting zone, the preplanned contingency plan are executed to recover the time delay. In CCPM the workers are asked to work with relay runner work mechanism that they work fast if possible and report their completion to project manager for the succeeding task to start as soon as possible. The task durations are not considered as the promised time schedule. The multi-tasking is prohibited.

• Journal of the Korea Society of Computer and Information
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• v.27 no.12
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• pp.17-27
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• 2022

In this paper, ED-H algorithm, an optimal real-time scheduling algorithm dealing with the characteristics of the integrated energy harvester system with a capacitor, is extended to satisfy the time constraint under the blackout state which is a deliberate power-off state by an intelligent power management unit adopted in the system. If the power supply system does not have enough energy, it temporarily shuts off the power supply to protect the circuit and capacitor and resumes the supply again when the capacitor is fully charged, which may delay the task execution during these blackout states by calculating the time according to the occurrence of the events. To mitigate the problem, even if task execution is delayed by the original ED-H algorithm, the remaining time of the subsequent time units no longer can afford to delay the execution of the task is predicted in the extended algorithm and the task is forced to be scheduled to meet the time deadline. According to the simulation results, it is confirmed that the algorithm proposed in this paper has a high scheduling performance increase of 0.4% to 7.7% depending on the characteristics of the set of tasks compared to the ED-H.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.7
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• pp.684-694
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• 2000

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Explosives and Blasting
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• v.34 no.4
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• pp.40-45
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• 2016

Sites, where explosives are used, are constantly under constraint of vibration and noise levels. If a sensitive area is located nearby the sites, mechanical excavation has been preferred rather than blasting. Recently, however, blasting using electronic detonators is applicable in the areas, where previously should be excavated by mechanical methods. $HiTRONIC^{TM}$ is a fourth-generation detonator that utilizes Hanwha Corporation's advanced electronic technology. The detonator contains IC-Chip, which allows delay times between 0~15,000ms with 1ms interval. Furthermore, the product can provide high accuracy(0.01%) for accurate-blasting. Electronic detonator is widely used in highway and railway construction sites, large limestone quarries, and other works. In this paper, several sites, in which HiTRONIC was used, are introduced in order to enhance understanding of electronic detonator.

• Journal of Advanced Navigation Technology
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• v.13 no.5
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• pp.742-748
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• 2009

Zigbee wireless communication technology has features which are low cost, low power and coping ability against a high delay time when the automatic wireless system is manufactured. Therefore, in this paper, we research a method improving the data transmission reliability of the industrial equipment control and management system using zigbee wireless communication technology. we used a convolutional code with code rate R=1/2, constraint K=5 and generation polynomial constant g1=(10111) and g2=(10011) as a reliability method. From the transmission simulation at LOS environment, we are able to predict the transmission error performance according to the distance difference. Furthermore, At the PER performance analysis, we can get the result that this system reliability with convolutional code is improved about 5 times than the existing system. From these results, we can prove that the convolutional code is the solution to improve the system reliability of the industrial equipment control and management system using zigbee wireless communication technology.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.6
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• pp.131-140
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• 2009

A key challenge for Wireless Body Area Network (WBAN) is to maximize the network lifetime with power-efficient and flexible duty cycling techniques on energy-constraint sensor nodes. In this paper, we propose a novel power-efficient MAC protocol for WBAN that accommodates normal, emergency, and on-demand traffic in a reliable manner. This protocol supports two wakeup mechanisms, a traffic-based wakeup mechanism, which accommodates normal traffic by exploiting the node's traffic patterns, and a wakeup radio mechanism, which accommodates emergency and on-demand traffic by using a wakeup radio. It can be seen that the proposed protocol not only improves the lifetime of WBAN but also provides a reliable method to handle sporadic events. Simulation results show that the proposed protocol outperforms WiseMAC in terms of low-power consumption and delay.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.49-54
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• 2016

Data delivery is very challenging in VANETs because of its unique characteristics, such as fast topology change, frequent disruptions, and rare contact opportunities. This paper tries to explore the scope of 3G-assisted data delivery in a VANET within a budget constraint of 3G traffic. It is started from the simple S_Random (Srand) and finally reached the 3GSDD, i.e., the proposed algorithm. The performance evaluation of different algorithms is done through the two metrics delivery ratio and average delay. A third function utility is created to reflect the above two metrics and is used to find out the best algorithm. A packet can either be delivered via multihop transmissions in the VANET or via 3G. The main challenge is to decide which set of packets should be selected for 3G transmissions and when to deliver them via 3G. The aim is to select and send those packets through 3G that are most sensitive and requiring immediate attention. Through appropriate communication mechanism, these sensitive information are delivered via VANET for 3G transmissions. This way the sensitive information which could not be transmitted through normal VANET will certainly find its destination through 3G transmission unconditionally and with top priority. The delivery ratio of the packets can also be maximized by this system.