• Journal of Information Technology Services
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• v.10 no.3
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• pp.203-212
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• 2011

In the every day life of the people, the Internet is widely used. Currently over 1.9 billion people have one or more email addresses and over 600 million people use the Facebook. People are collaborating via the Internet more and more. When people are collaborating through the Internet, the differences of the message delivery delay are the biggest problem that disturbs the collaborative work over the network. To solve the differences of the message delivery delay, we introduce the delay-gap method. An experimental code have been implemented and the efficiency of the delay-gap is presented through the results from the experiment that have many participants.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.62-67
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• 2001

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need a large time delay over the reception process. Moreover, Turbo Code has been known as the robust ending method with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications such as IMT-2000. Therefore, in this paper, we proposed of the method to improve the conventional performance with the parallel concatenated 4-New Turbo Decoder using MAP a1gorithm in spite of complexity increasement. In the real-time video and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and fading channels.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.69-72
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• 1997

A universal controller is designed using a DSP (digital signal processor). The design objectives of the system are to implement control algorithms that require a lot of calculations and to develop a convenient user-interface environment. To demonstrate the efficiency of the system, the time delay control algorithm is implemented for the 2 D.O.F.SCARA type robot and the experimental results are presented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.937-949
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• 1988

This paper proposes a code optimization algorithm for dealing with hazards which are occurred in pipelined architecture due to resource dependence between executed instructions. This algorithm solves timing hazard which results from resource conflict between concurrently executing instructions, and sequencing hazard due to the delay time for branch target decision by reconstructing of instruction sequence without pipeline interlock. The reconstructed codes can be generated efficiently by considering timing hazard and sequencing hazard simultaneously. And dynamic execution time of program is improved by considering structral hazard which can be existed when pipeline is controlled dynamically.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.112-114
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• 2009

In this paper, a PN code tracking loop with extended Kalman filter (EKF) is proposed for a direct-sequence spread-spectrum. EKF is used to estimate amplitude and delay in a multipath fading channel. It is shown that tracking error performance is significantly improved by EKF compared with a conventional tracking loop.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1872-1878
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• 2000

Turbo Code는 반복 부호 알고리듬을 사용함으로써 백색 가우시안 잡음(AWGN)채널 환경하에서 Shannon의 한계에 가까운 성능을 보이는 오류정정 방식으로 제안되었다. 그러나 Turbo code는 반복복호로 인해 매 복호시마다 큰 인터리버와 복호기를 거쳐야 하기 때문에 수신과정에서 커다란 지연을 요구하게 된다. 따라서 차세대 무선 멀티미디어 통신에서 실시간 음성서비스나 화상서비스를 제공하는데 어려움이 많다. 본 논문에서는 기존의 터보 복호기를 변형하여 매 복호시 각각의 복호기에서 LLR 출력시퀀스를 발생시킴으로써 반복 복호 횟수를 줄이는 방법을 제안하였다. 이렇게함으로서 기존의 Toubo code가 갖는 성능은 크게 변화시키지 않으면서 각각의 정보프레임을 가변적으로 복호함으로서 반복 복호로 인한 시간 지연을 줄였다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.597-600
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• 2000

Turbo Code는 반복 복호알고리듬을 사용함으로써 백색 가우시안 잡음(AWGN)채널 환경에서 Shannon의 한계에 가까운 성능을 보이는 오류정정 방식으로 제안되었다. 그러나 Turbo code는 반복복호로 인해 매복호시마다 큰 인터리버와 복호기를 거쳐야 하기 때문에 수신과정에서 커다란 지연을 요구하게 된다. 따라서 차세대 무선 멀티미디어 통신에서 실시간으로 음성서비스나 화상서비스를 제공하는데 어려움이 많다. 본 논문에서는 기존의 터보 복호기를 변형하여 매 복호시 각각의 복호기에서 출력시퀀스를 발생시킴으로서 반복 복호 횟수를 줄이는 방법을 제안하였다. 이렇게 함으로서 기존의 Turbo code가 갖는 성능은 크게 변화시키지 않으면서 각각의 정보프레임을 가변적으로 복호함으로서 반복복호로 인한 시간 지연을 줄일수 있었다.

• Journal of Advanced Marine Engineering and Technology
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• v.25 no.2
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• pp.375-382
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• 2001

In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.