• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.426-429
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• 2003

In the construction process, there are many change orders differing to the initial contracts came from the social needs and environmental changes. Most of them will impact to the construction process so that its effects occur project delays. Time extension and liquidated damage in the construction process come from schedule delay whether it is excusable or not non-excusable by the owner. However, those become the delay claims if the owner and the contractor are not agreed on this situation. One of the most important thing on the delay claims is the calculation of delay. The purpose of this study is to present the method of the time delay calculation by comparison of As-Planned schedule, As-Built schedule including all delay and As-Built schedule absent owner delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.486-495
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• 2002

In this paper, we propose a delay reduction method for frame-based packet transmit scheduling algorithm. A high-speed network such as ATM network has to provide some performance guarantees such as bandwidth and delay bound. Framing strategy naturally guarantees bandwidth and enables simple rate-control while having the inherently bad delay characteristics. The proposed delay reduction method uses the same hierarchical frame structure as HRR (Hierarchical Round-Robin) but does not use the static priority scheme such as round-robin. Instead, we use a dynamic priority change scheme so that the delay unfairness between wide bandwidth connection and narrow bandwidth connection can be eliminated. That is, we use FIFO (First-In First-Out) concept to effectively reduce the occurrence of worst-case delay and to enhance delay distribution. We compare the performance for the proposed algorithm with that of HRR. The analytic and simulation results show that HFIFO inherits almost all merits of HRR with fairly better delay characteristics.

• Korean Journal of Culture and Social Issue
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• v.20 no.4
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• pp.347-364
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• 2014

The present study was conducted to investigate how emotional expression change, test delay, and background influence on face recognition. In experiment 1, participants were presented with negative faces at study phase and administered for standard old-new recognition test including targets of negative and neutral expression for the same faces. In experiment 2, participants were studied negative faces and tested by old-new face recognition test with targets of negative and positive faces. In experiment 3, participants were presented with neutral faces at study phase and had to identify the same faces with no regard for negative and neutral expression at face recognition test. In all three experiments, participants were assigned into either immediate test or delay test, and target faces were presented in both white and black background. Results of experiments 1 and 2 indicated higher rates for negative faces than neutral or positive faces. Facial expression consistency enhanced face recognition memory. In experiment 3, the superiority of facial expression consistency were demonstrated by higher rates for neutral faces at recognition test. If facial expressions were consistent across encoding and retrieval, memory performance on face recognition were enhanced in all three experiments. And the effect of facial expression change have different effects on background conditions. The findings suggest that facial expression change make face identification hard, and time and background also affect on face recognition.

• Journal of the korean Society of Automotive Engineers
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• v.5 no.2
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• pp.41-47
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• 1983

The analysis shows that the variation of maximum pressure of the cycle, rate of hear release, rate of mass burned, and combustion delay are influenced by the inlet air humidity in the spark-ignition engine. The quantitative combustion delay can be obtained from the rate of mass burned. Also, the variation of time loss and effective compression ratio with the change of inlet air humidity are dominated by the development of rate of heat release.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.216-221
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• 2002

A spherical Earth surface is used fur realistic analysis of the geometrical performance characteristics about the variation of satellite altitude and 2-dimensional line-of-sight(LOS) tilt angle in a satellite imager using Time Delay and Integration(TDI) technique with fixed integration time. In the spherical Earth surface model TDI synchronization using LOS tilt is investigated as a solution to compensate geometric performance degradation due to altitude decrease. This result can be used fur a TDI CCD imager with variable integration time in a certain as well.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2641-2647
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• 2003

Conventional DLLs estimate the delay times of satellite signals individually and feed back these measurements to the VCO independently. But VDLL estimates delay times and user position directly and then estimate the feedback term for VCO using the estimated position changes. In this process, input measurements are treated as vectors and these vectors are used for navigation. First advantage of VDLL is that noise is reduced in all of the tracking channels making them less likely to enter the nonlinear region and fall below threshold. Second is that VDLL can operate successfully when the conventional independent parallel DLL approach fails completely. It means that VDLL receiver can get enough total signal power to track successfully to obtain accurate position estimates under the same conditions where the signal strength from each individual satellite is so low or week that none of the individual scalar DLL can remain in lock when operating independently. To operate VDLL successfully, it needs to know the initial user dynamics and position and prevents total system from the divergence. The suggested integration method is to use the inertial navigation system to provide initial dynamics for VDLL and to maintain total system stable. We designed the GPS/INS integrated navigation system. This new type of integrated system contained the vector pseudorange format generation block, VDLL signal processing block, position estimation block and the conversion block from position change to delay time feedback term aided by INS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.5-10
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• 2005

We deal with the sliding mode control using the time delay estimation. The time delay estimation is able to weaken the need for obtaining a quantitative plant model analogous to the real plant so the sliding mode control with a time delay estimation (SMCTE) is very suitable for plant such as SMA actuators whose quantitative model is difficult to obtain. We have already studied the application of the time delay control (TDC) to SMA actuators in other literature. Based on the previous study on the TDC, we developed the gain tuning method for the SMCTE, which results were nearly the same as the TDC. With respect to the step response, the SMCTE proved its predominance in a comparison with other control schemes such as the PID control and the relay control. As well as the contribution of the above control methodology, the model identification for SMA actuators has also been studied. The dynamics for an SMA actuator was newly derived using the modified Liang's model. The derived dynamics showed a continuity at the change of the phase transformation process but the original Liang's model could not.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.22-27
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• 2009

Bilateral teleoperation systems, connected to computer networks such as Internet have to deal with the time delay depending on factors such as congestion, bandwidth or distance. And the entire system is easy to become unstable due to irregular time delay. Passivity concept has been using as a framework to solve the stability problem in bilateral control of teleoperation. In this paper, we present a suitable time varying gain inserted in the transmission path that can recover passivity provided a bound on the rate of change of the known delay. Simulation results are presented showing the performance of the resulting control architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.