• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1149-1152
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• 1999

In this paper we analyzed each region of specific points and ｅ-Δｅphase plane in order to make fuzzy rule base. After we composed the fuzzy control rules which can decrease rise time, delay time, maximum overshoot than basic fuzzy control rules. The composed method are converged more rapidly than single rule base in convergence region. Proposed method is alternately use at specific points of ｅ-Δｅphase plane with two fuzzy control rules, that is one control rule occruing the steady state error used in transient region and another fuzzy control rule use to decrease the steady state error and rapidly converge at the convergence region. Two fuzzy control rules in the ｅ-Δｅ phase plane decide the change time according to response characteristics of plants. As the results of simulation through the second order plant and the delay time plan, Proposed dual fuzzy control rules get the good response compare with the basic fuzzy control rule.

• 센서학회지
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• 제19권2호
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• 한국군사과학기술학회지
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• 제11권3호
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• pp.40-49
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• 2008

In this paper, we have described a Simulated Radar Target Generation Equipment(SRTGE) for evaluating the performance of a developed radar system. In order to change a simulated target range(or time delay), the variable optical delay line structure is used in SRTGE, In addition, SRTGE is required to generate a target return signal which is composed of variable amplitude and Doppler velocity. The interference such as noise jamming and clutter is also produced from SRTGE for evaluating ECCM(Electronic-Counter-Counter Measure) capability of radar.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.426-429
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• 2002

The data link layer (DLL) of Foundation Fieldbus (FF) includes both token-passing and scheduling services. Periodic data are transmitted via the scheduling service, while time-critical and time-available data are transmitted via the token-passing service. This study developed a network interface board that implements the DLL of FF. Using the network interface board, this study experimentally evaluates the delay performance of the DLL of FF. This study measured the delay performance with respect to the change of the DLL parameters of FF, and investigated the relationship between the DLL parameters and network performance. The study also compared the experimental results with the results obtained from an analytical model.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.714-716
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• 2005

We studied the dependence of the electrical characteristics of MgO protecting layer on temperature in an AC PDP cell. Careful measurements of the surface resistance of MgO were performed for the temperature range from room temperature to $100^{\circ}C$ with and without the VUV illumination. Experimental results show that the resistivity is affected by not only the temperature but also VUV irradiation. The measurement of wall charge distribution and the address discharge delay time as to the temperature show that the resistivity change of MgO may affect the wall voltage and consequently the discharge delay time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.257-258
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• 2007

In real-time video communications, the large fluctuation of bits generated from contiguous frames may lead to the buffer oveflow and the delay of transmitting video data. This paper proposes a method that the bits generated from each frame may be in the range of specified fluctuation. The method uses a scene change detector and ignores the time information of detected frames. The experimental results indicate that our scheme achieves average PSNR gain of 2.0dB over TMN8.

• 대한산업공학회지
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• 제37권3호
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• pp.229-233
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• 2011

The existing approaches for analyzing the data service capacity of CDMA2000 1X EV-DO (Evolution-Data Only) systems have focused on deriving the maximum number of active customers assuming that the data rates provided to the customers can be determined beforehand. However, we have seen that through real experiment, the data rates actually provided to the customers adaptively change according to the number of active customers. In this paper, we propose new capacity analysis model considering the data rate adaptation. Numerical examples are also presented to obtain the maximum input traffic rates for various values of the length of data burst and the required mean delay bound.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.179-181
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• 1998

In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권3호
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• pp.1599-1610
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• 2019

Intelligent services have expanded as Internet of Things (IoT) technology has evolved and new requirements emerge to accommodate various services. One new requirement is transmitting data over long distances with low-power. Researchers have developed low power wide area (LPWA) network technology to satisfy the requirement; this can improve IoT network infrastructure and increase the range of services. However, network coverage expansion causes several problems. The traffic load is concentrated at a specific gateway, which causes network congestion and leads to decreased transmission efficiency. Therefore, the approach proposed in this paper attempts to recognize and then avoid congestion through gateway channel hopping. The LPWA network employs multiple channels, so wireless channel hopping is available in a gateway. Devices that are not delay sensitive wait for the gateway to reappear on their wireless channel; delay sensitive devices change the wireless channel along the hopping gateway. Thus, the traffic load and congestion in each wireless channel can be reduced improving transmission efficiency. The proposed approach's performance is evaluated by computer simulation and verified in terms of transmission efficiency.