• Journal of the Korean Vacuum Society
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• v.21 no.4
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• pp.219-224
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• 2012

We study for long-term performance of amorphous silicon solar cells under light exposure. The performance is predicted with a kinetic model in which the carrier lifetimes are determined by the defect density. In particular, the kinetic model is described by the stretched-exponential relaxation of defects to reach equilibrium. In this report, we simulate the light-induced degradation of the amorphous silicon solar cells with the kinetic model and AMPS-1D computer program. And data measured for outdoor performances of various solar cells are compared with the simulated results. This study focuses on examining the light-induced degradation for the following amorphous silicon pin solar cells: thickness${\approx}$300 nm, built-in potential${\approx}$1.05 V, defect density (at t=0)${\approx}5{\times}10^{15}cm^{-3}$, short-circuit current density (at t=0)${\approx}15.8mA/cm^2$, fill factor (at t=0)${\approx}0.691$, open-circuit voltage (at t=0)${\approx}0.865V$, conversion efficiency (at t=0)${\approx}9.50%$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.329-329
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• 2016

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.3
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• pp.371-385
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• 1995

The yield of semiconductor chips is dependent not only on the average defect density but also on the distribution of defects over a wafer. The distribution of defects leads to consider a cluster index. This paper briefly reviews the existing yield prediction models ad proposes a new cluster index, which utilizes the information about the defect location on a wafer in terms of the coefficient of variation. An extensive simulation is performed under a variety of defect distributions and a yield prediction model is derived through the regression analysis to relate the yield with the proposed cluster index and the average number of defects per chip. The performance of the proposed simulation-based yield prediction model is compared with that of the well-known negative binomial model.

• Journal of the Korean Ceramic Society
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• v.19 no.4
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• pp.300-308
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• 1982

A new perovskite type compound, (Pb1a-χKy□χ-y) (Zr0.33Ti0.67)O3-χ+y/2 was proposed and synthesized by "Wet-Dry Combination Technique". This defect ferroelectric material was characterized by partial substitutions of K+ for Pb+2 in Pb(Zr0.33Ti0.67)O3. This material was mono-phasic perovskite compound at 800℃ for 1hr., but ZrO2 was more or less isolated from the (Pb1a-χKy□χ-y) (Zr0.33Ti0.67)O3-χ+y/2. As a result, snitering temperature, sintered density, curie temperature, and dielectric constant of test pieces decreased and a-axis was nearly constant, while c-axis gradually decreased with the value x in the region of tetragonal phase of PZT. It was also recognized that the defect structure caused by adding K+ was found in both A-site cation and O-site anion vacancies in the defect PZT.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• Journal of the Korean Ceramic Society
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• v.34 no.8
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• pp.843-853
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• 1997

The effect of dopant on microwave dielectric properties of (1-x)MgTiO3-xCaTiO3 ceramics, known to be used as microwave dielectric resonators for global positioning system and personal communication system, has been analyzed in terms of variations in defect concentrations and microstructural features with its addition. The addition of dopants was revealed to result in a significant change in the microstructure as well as defect concentration of the ceramics. For instance, the quality factor is proportional to sintered density of the ceramics by inversely proportional to grain size as well as vacancy concentration. Accordingly, it is believed that the dopant effect on the microwave dielectric properties should be separately analyzed with either microstructural change or the change in vacancy concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.939-942
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• 2016

One of the most important characteristic curves of a solar cell is its current density-voltage (J-V) curve under AM1.5G insolation. Solar cell can be considered as a semiconductor diode, so a diode equivalent model was used to estimate its parameters from the J-V curve by numerical simulation. Active layer plays an important role in operation of a solar cell. We investigated the effect thicknesses and defect densities (N_d) of the active layer on the J-V curve. When the active layer thickness was varied (for N_d = 8×10¹⁷ cm^-3) from 800 nm to 100 nm, the reverse saturation current density (J_o) changed from 3.56×10^-5 A/cm² to 9.62×10^-11 A/cm² and its ideality factor (n) changed from 5.28 to 2.02. For a reduced defect density (N_d = 4×10¹⁵ cm^-3), the n remained within 1.45≤n≤1.92 for the same thickness range. A small increase in shunt resistance and almost no change in series resistance were observed in these cells. The low reverse saturation current density (J_o = 9.62×10^-11 A/cm²) and diode ideality factor (n = 2.02 or 1.45) were observed for amorphous silicon based solar cell with 100 nm thick active layer.