• 전자공학회논문지A
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• 제33A권7호
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• pp.198-204
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• 1996

Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.212-215
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• 2005

Modified illumination techniques have been used to enhance the resolution of the sub-wavelength lithography. But, since they shield the central part of incident light, the light efficiency is seriously degraded, which in turn reduces the throughput of a lithography process. In this research, we introduced an annular illumination structure that enhances the light efficiency with a concentric circular grating at the backside of a photomask. The efficiency of the structure was theoretically analyzed.

• 전자공학회논문지A
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• 제31A권10호
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• pp.101-107
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• 1994

The PMMA/Ge/AZ trilayer resist decreased proximity effect of backscattering electrons and corrected pattern distoration in order to from deep submicron patterns. In the experiment, the prosiemity effect is decreased by 11% and 30% for the case of 0.9$\mu$m and 1.7$\mu$m AZ, respectively, in trilayer resist compared to monolyer resist. also, the EID of 240$\AA$ Ge film is smaller than that of 500$\AA$ film by 365. 0.1$\mu$m line/space was formed in the 2000$\AA$ PMMA layer with the condition of dose 330${\mu}C/cm^{2}$ and of 150sec of develop time in MIBK : IPA (1:3) developer.

• 한국전기전자재료학회논문지
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• 제17권7호
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• pp.697-700
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• 2004

We propose a method that realizes the modified illumination by implementing a binary phase grating at the backside of a photomask. By modeling the relationship between the shape of a grating on the photomask and the light intensity at the pupil plane, we developed a program named MIDAS that finds the optimum grating pattern with a stochastic approach. After applying the program to several examples, we found that the program finds the grating pattern for the modified illumination that we want. By applying the grating at the backside of a photomask, the light efficiency of modified illumination may be improved.

• 한국광학회지
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• 제4권1호
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• pp.1-8
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• 1993

축소배율(5$\times$)을 갖고, Seidel 1차 수차중 4개의 비축수차인 코마(coma), 비점수차(astigmatism), 상면만곡(field curvature) 그리고 왜곡수차(distortion)가 제거된 마이크로 리소그라피를 위한 4-구면 반사경 광학계를 해석적으로 구하였다. 이때, $t=d_1+d_2+d_3$<0, (di는 반사거울 $c_i$와 $c_{i+1}$ 사이의 거리)이고, 축상 수차인 구면수차와 잔류고차수차는 반사거울 $c_3$와 $c_4$를 비구면화 하므로서 제거하였다. 이렇게 설계된 4-반사경 광학계의 N.A.는 0.4로서 Rayleigh분해능은 0.38 $\mu\textrm{m}$이다.

• ETRI Journal
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• 제14권1호
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• pp.52-65
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• 1992

전자선 직접묘사 (E-beam direct writing lithography) 방법을 이용하여 $0.2\mum$ 과 $0.3\mum$ 의 게이트길이를 가지는 NMOS 트랜지스터를 제작하였다. 게이트만 전자선 직접묘사 방법으로 정의하고 나머지는 optical stepper를 이용하는 Mix & Match 방식을 사용하였다. 게이트산화막의 두께는 최소 6nm까지 성장시켰으며, 트랜지스터구조로서는 lightly-doped drain(LDD) 구조를 채택하였다. 짧은 채널효과 및 punch through를 줄이기 위한 방안으로 채널에 깊이 붕소이온을 주입하는 방법과 well을 고농도로 도핑하는 방법 및 소스와 드레인에 $p^-$halo를 이온주입하는 enhanced lightly-doped drain(ELDD) 방법을 적용하였으며, 제작후 성능을 각각 비교하였다. 제작된 $0.2\mum$의 게이트길이를 가지는 소자에서는 문턱전압과 subthreshold기울기는 각각 0.69V 및 88mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance와 포화 드레인전류는 각각 200mS/mm, 0.6mA/$\mum$이었다. $0.3\mum$소자에서는 문턱전압과 subthreshold 기울기는 각각 0.72V 및 82mV/dec. 이었으며, Vds=3.3V에서 측정한 포화 transconductance는 184mS/mm이었다. 이러한 결과는 전원전압이 3.3V일 때 실제 ULSI에 적용가능함을 알 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.569-572
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• 1998

The semiconductor technology for the deep submicron $regime(0.18\mu\textrm{m})$ and larger wafer $diameters(300\mu\textrm{m})$ has been increased its cost with each wafer. Hence, in order to reduce the number of characterization experiments of a new process, lithographic modeling is more important than it was. In this paper, we introduced a new method to extract Dill ABC parameters from the refractive index changes. In order to evaluate our exact method, results of experiments and calculations for several resists were compared with other methods〔1〕through the lithographic simulation.