• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3056-3074
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• 2014

Convergecast is probably the most common communication style in wireless sensor networks (WSNs). And linear network coding (LNC) is a promising concept to improve throughput or reliability of convergecast. Most of the existing works have mainly focused on exploiting these benefits without considering its potential adverse effect. In this paper, we argue that LNC may not always benefit convergecast. This viewpoint is discussed within four basic scenarios: LNC-aided and none-LNC convergecast schemes with and without automatic repeat request (ARQ) mechanisms. The most concerned performance metrics, including packet collection rate, energy consumption, energy consumption balance and end-to-end delay, are investigated. Theoretical analyses and simulation results show that the way LNC operates, i.e., conscious overhearing and the prerequisite of successfully decoding, could naturally diminish its advantages in convergecast. And LNC-aided convergecast schemes may even be inferior to none-LNC ones when the wireless link delivery ratio is high enough. The conclusion drawn in this paper casts a new light on how to effectively apply LNC to practical WSNs.

• Clinical and Experimental Pediatrics
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• v.65 no.5
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• pp.239-249
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• 2022

Cells survive and proliferate through complex interactions among diverse molecules across multiomics layers. Conventional experimental approaches for identifying these interactions have built a firm foundation for molecular biology, but their scalability is gradually becoming inadequate compared to the rapid accumulation of multiomics data measured by high-throughput technologies. Therefore, the need for data-driven computational modeling of interactions within cells has been highlighted in recent years. The complexity of multiomics interactions is primarily due to their nonlinearity. That is, their accurate modeling requires intricate conditional dependencies, synergies, or antagonisms between considered genes or proteins, which retard experimental validations. Artificial intelligence (AI) technologies, including deep learning models, are optimal choices for handling complex nonlinear relationships between features that are scalable and produce large amounts of data. Thus, they have great potential for modeling multiomics interactions. Although there exist many AI-driven models for computational biology applications, relatively few explicitly incorporate the prior knowledge within model architectures or training procedures. Such guidance of models by domain knowledge will greatly reduce the amount of data needed to train models and constrain their vast expressive powers to focus on the biologically relevant space. Therefore, it can enhance a model's interpretability, reduce spurious interactions, and prove its validity and utility. Thus, to facilitate further development of knowledge-guided AI technologies for the modeling of multiomics interactions, here we review representative bioinformatics applications of deep learning models for multiomics interactions developed to date by categorizing them by guidance mode.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.9
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• pp.381-392
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• 2013

During the last decade, the multitude of advances attained in terminal computers, along with the introduction of mobile hand-held devices, and the deployment of high speed networks have led to a recent surge of interest in Quality of Service (QoS) for video applications. The main difficulty is that mobile devices experience disparate channel conditions, which results in different rates and patterns of packet loss. One way of making more efficient use of network resources in video services over wireless channels with heterogeneous characteristics to heterogeneous types of mobile device is to use a scalable video coding (SVC). An SVC divides a video stream into a base layer and a single or multiple enhancement layers. We have to ensure that the base layer of the video stream is successfully received and decoded by the subscribers, because it provides the basis for the subsequent decoding of the enhancement layer(s). At the same time, a system should be designed so that the enhancement layer(s) can be successfully decoded by as many users as possible, so that the average QoS is as high as possible. To accommodate these characteristics, we propose an efficient transmission scheme which incorporates SVC-aware dual-channel repetition to improve the perceived quality of services. We repeat the base-layer data over two channels, with different characteristics, to exploit transmission diversity. On the other hand, those channels are utilized to increase the data rate of enhancement layer data. This arrangement reduces service disruption under poor channel conditions by protecting the data that is more important to video decoding. Simulations show that our scheme safeguards the important packets and improves perceived video quality at a mobile device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2281-2287
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• 2013

Network Coding(NC) is a new paradigm for network communication. In network coding, intermediate nodes create new packets by algebraically combining ingress packets and send it to its neighbor node by broadcast manner. Network Coding has rapidly emerged as a major research area in information theory due to its wide applicability to communication through real networks. Network coding is expected to improve throughput and channel efficiency in the wireless multi-hop network. Prior researches have been carried out to employ network coding to wireless ad-hoc network. In our study, intermediate nodes identify one-hop bidirectional flows for network coding decision. We expect that the proposed scheme shall improve decoding success rate of network coded packet. From the simulation, the proposed network coding scheme achieved better performance in terms of coding gain and packet delivery rate than traditional network coding scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.9-16
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• 2013

Long term evolution (LTE) and LTE-Advanced (LTE-A) systems adopt closed-loop multiple-input multiple-output antenna techniques. Equal gain transmission which has equal gain property is the key factor in their codebook design. In this paper, a novel differential codebook structure which maintains the codebook design requirements of LTE or LTE-A systems. Especially, eight-phase shift keying (8-PSK) constellations are used as elements of codewords, which not only maintain equal gain property but also reduce the computation complexity of precoding and decoding function blocks. The equal gain property is very important to uplink because the performance of uplink is very sensitive to the peak-to-average power ratio (PAPR). Moreover, the operation of the proposed differential codebook is explained as a rotation-lock structure. As the results of computer simulations, the steady-state throughput performance of the proposed codebook shows at least 0.9dB of SNR better than those of the conventional LTE codebook with the same amount of feedback information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1786-1792
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• 2015

Random linear network coding (RLNC) is widely employed to enhance the reliability of wireless multicast. In RLNC encoding/decoding, Galois Filed (GF) arithmetic is typically used since all the operations can be performed with symbols of finite bits. Considering the architecture of commercial computers, the complexity of arithmetic operations is constant regardless of the dimension of GF m, if m is smaller than 32 and pre-calculated tables are used for multiplication/division. Based on this, we show that the complexity of RLNC inversely proportional to m. Considering additional overheads, i.e., the increase of header length and memory usage, we determine the practical value of m. We implement RLNC in a commercial computer and evaluate the codec throughput with respect to the type of the tables for multiplication/division and the number of original packets to encode with each other.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.