• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.6
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• pp.48-56
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• 2010

Recently, we need to dramatically speed up real-time video encoding and decoding on mobile devices because complexity of video CODEC is significantly increasing along with the demand for multimedia service of high-quality and high-definition videos by users. A variety of research is conducted for parallelism of video processing using newly developed multi-core platforms. In this paper, we propose a method of parallelism based on slice partition of video compression CODEC. We propose a novel concept of a parallel slice for parallelism and propose a new coding order to be adequate to the parallel slice which keeps high coding efficiency. To minimize synchronization time of multiple parallel slices, we also propose a synchronization method to determinate whether the parallel slice could be independently decoded or not. Experimental results shows that we achieved 27.5% (40.7%) speed-up by parallelism with bit-rate increase of 3.4% (2.7%) for CIF sequences (720p sequences) by implementing the proposed algorithm on the H.264/AVC.

• Journal of Broadcast Engineering
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• v.13 no.2
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• pp.188-199
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• 2008

In conventional video coding, encoder complexity is much higher than that of decoder. However, investigations for lightweight encoder to eliminate motion prediction/compensation claiming most complexity in encoder have recently become an important issue. The Wyner-Ziv coding is one of the representative schemes for the problem and, in this scheme, since encoder generates only parity bits of a current frame without performing any type of processes extracting correlation information between frames, it has an extremely simple structure compared to conventional coding techniques. However, in Wyner-Ziv coding, channel decoding errors occur when noisy side information is used in channel decoding process. These channel decoding errors appear more frequently, especially, when there is not enough correlation between frames to generate accurate side information and, as a result, those errors look like Salt & Pepper type noise in the reconstructed frame. Since this noise severely deteriorates subjective video quality even though such noise rarely occurs, previously we proposed a computationally extremely light encoding method based on selective median filter that corrects such noise using spatial correlation of a frame. However, in the previous method, there is a problem that loss of texture from filtering may exceed gain from error correction by the filter for video sequences having complex torture. Therefore, in this paper, we propose an improved lightweight encoding method that minimizes loss of texture detail from filtering by allowing information of texture and that of noise in side information to be utilized by the selective median filter. Our experiments have verified average PSNR gain of up to 0.84dB compared to the previous method.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.575-582
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• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.756-764
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• 2012

In current HEVC, prediction pixels are finally calculated by linear-function interpolation on two reference pixels. It is hard to expect good performance on the case of occurring large difference between two reference pixels. This paper decides more accurate prediction pixel values than current HEVC using linear function. While existing prediction process only uses two reference pixels, proposed method uses DCT-IF. DCT-IF analyses frequency characteristics of more than two reference pixels in frequency domain. And proposed method calculates prediction value adaptively by using linear-function, DCT-IF and cubic-function to decide more accurate interpolation value than to only use linear function. Cubic-function has a steep slope than linear-function. So, using cubic-function is utilized on edge in prediction unit. The complexity of encoder and decoder in HM6.0 has increased 3% and 1%, respectively. BD-rate has decreased 0.4% in luma signal Y, 0.3% in chroma signal U and 0.3% in chroma signal V in average. Through this experiment, proposed adaptive intra prediction method using DCT-IF and cubic-function shows increased performance than HM6.0.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.98-106
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• 2011

Since prediction processes such as motion estimation motion compensation are not at the WZ video encoder but at its decoder, WZ video compression cannot have better performance than that of conventional video encoder. In order to implement the prediction process with low complexity at the encoder, WZ residual coding was proposed. Instead of original WZ frames, WZ residual coding encodes the residual signal between key frames and WZ frames. Although the proposed WZ residual coding has good performance in pixel domain, it does not have any improvements in transform domain compared to transform domain WZ coding. The WZ residual coding in transform domain is difficult to have better performance, because pre-defined quantization matrices in WZ coding are not compatible with WZ residual coding. In this paper, we propose a new quantization method modifying quantization matrix and quantization step size adaptively for transform domain WZ residual coding. Experimental result shows 22% gain in BDBR and 1.2dB gain in BDPSNR.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9A
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• pp.1290-1298
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics, and uses the information to the next decoding step Turbo Code shows excellent performance, approaching Shannon Limit at the view of BER, when the size of Interleaver is big and iterate decoding is run enough. But it has the problems which are increased complexity and delay and difficulty of real-time processing due to Interleaver and iterate decoding. In this paper, it is analyzed that MAP(maximum a posteriori) algorithm which is used as one of Turbo Code decoding, and the factor which determines its performance. MAP algorithm proceeds iterate decoding by determining soft decision value through the environment and transition probability between all adjacent bits and received symbols. Therefore, to improve the performance of MAP algorithm, the trust between adjacent received symbols must be ensured. However, MAP algorithm itself, can not do any action for ensuring so the conclusion is that it is needed more algorithm, so to decrease iterate decoding. Consequently, MAP algorithm and Turbo Code performance are analyzed in the nongaussian channel applying Robust equalization technique in order to input more trusted information into MAP algorithm for the received symbols.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.40-47
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• 2007

In this paper, we propose and analyze the Adaptive Modulation System with optimal Turbo Coded V-BLAST(Vertical-Bell-lab Layered Space-Time) technique that adopts the extrinsic information from MAP (Maximum A Posteriori) Decoder with Iterative Decoding as a priori probability in two decoding procedures of V-BLAST; the ordering and the slicing. Also, we consider and compare the Adaptive Modulation System using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme and the Adaptive Modulation System using conventional Turbo Coded V-BLAST technique that is decoded by the ML (Maximum Likelihood) decoding algorithm. We observe a throughput performance and a complexity. As a result of a performance comparison of each system, it has been proved that the complexity of the proposed decoding algorithm is lower than that of the ML decoding algorithm but is higher than that of the conventional V-BLAST decoding algorithm. however, we can see that the proposed system achieves a better throughput performance than the conventional system in the whole SNR (Signal to Noise Ratio) range. And the result shows that the proposed system achieves a throughput performance close to the ML decoded system. Specifically, a simulation shows that the maximum throughput improvement in each MIMO scheme is respectively about 350 kbps, 460 kbps, and 740 kbps compared to the conventional system. It is suggested that the effect of the proposed decoding algorithm accordingly gets higher as the number of system antenna increases.