• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.11-21
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• 2008

In conventional video coding, the complexity of encoder is much higher than that of decoder. However, as more needs arises for extremely simple encoder in environments having constrained energy such as sensor network, much investigation has been carried out for eliminating motion prediction/compensation claiming most complexity and energy in encoder. The Wyner-Ziv coding, one of the representative schemes for the problem, reconstructs video at decoder by correcting noise on side information using channel coding technique such as turbo code. Since the encoder generates only parity bits without performing any type of processes extracting correlation information between frames, it has an extremely simple structure. However, turbo decoding errors occur in noisy side information. When there are high-motion or occlusion between frames, more turbo decoding errors appear in reconstructed frame and look like Salt & Pepper noise. This severely deteriorates subjective video quality even though such noise rarely occurs. In this paper, we propose a computationally extremely light encoder based on symbol-level Wyner-Ziv coding technique and a new corresponding decoder which, based on a decision whether a pixel has error or not, applies median filter selectively in order to minimize loss of texture detail from filtering. The proposed method claims extremely low encoder complexity and shows improvements both in subjective quality and PSNR. Our experiments have verified average PSNR gain of up to 0.8dB.

• Journal of information and communication convergence engineering
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• v.4 no.2
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• pp.79-83
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• 2006

We present two techniques based on lookup tables to reduce complexity of the well-known Schnorr-Euchner (SE) sphere decoder (SD) without introducing performance degradation. By the aid of lookup tables, the computational loads caused by the SE enumeration and decision feedback are reduced at the cost of higher storage capacity. Simulation results are provided to verify performance and complexity of the proposed decoders.

• Speech Sciences
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• v.11 no.2
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• pp.227-235
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• 2004

In this paper, we proposed a new practical implementation method of the lattice transversal joint (LTJ) adaptive filter using speech codec's information. And it was applied to the adaptive echo cancellation problem to verify the efficiency of the proposed method. Realtime implementation of the LTJ adaptive filter is very difficult due to high computational complexity for the filter coefficients compensation. However, in case of using speech codec, complexity can be reduced since linear predictive coding (LPC) coefficients are updated each frame or sub-frame instead of every sample. Furthermore, LPC coefficients can be acquired from speech decoder and transformed to the reflection coefficients. Therefore, the computational complexity for updates of the reflection coefficients can be reduced. The effectiveness of the proposed LTJ adaptive filter was verified by the experiments about convergence and tracking performance of the adaptive echo canceller.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2039-2042
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• 2002

In this paper, we propose a technique used to simplify the trellis diagram, thus, reduce the complexity of Viterbi decoder in term of the number of Compare-Select (CS) operations needs in decoding process. It is shown that if the branch metrics are properly decomposed into orthogonal components. The trellis diagram can be modified that each original state with large number branches terminating to it can be broken into a number of sub-states having smaller number of branches terminating to them. Simulation results shown that the newly proposed technique can be used reduced the complexity of 8 and 16 PSK-TCMs without degrading the BER performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.120-124
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• 2006

We present two techniques based on lookup tables to reduce complexity of the well-known Schnorr-Euchner (SE) sphere decoder (SD) without introducing performance degradation. By the aid of lookup tables, the computational loads caused by the SE enumeration and decision feedback are reduced at the cost of higher storage capacity. Simulation results are provided to verify performance and complexity of the proposed decoders.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• Journal of Broadcast Engineering
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• v.8 no.4
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• pp.481-491
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• 2003

We present a near-optimal blind decision feedback equalizer (DFE) for Advanced Television Systems Committee digital television (DTV) receivers. By adopting a modified trellis decoder (MTD) with trace back depth of 1 for the decision device In the DFE, we obtain a hardware-efficient near-optimal blind DFE approaching to the optimal DFE which has no error propagation. The MTD uses absolute distance instead of Euclidean distance for computation of a path metric, resulting. In reduced computational complexity. Comparing to the conventional slicer, the MTD shows outstanding performance improvement of decision error probability and is comparable to the original trellis decoder using Euclidean distance. Reducing error propagation in the DFE leads to the improvement of convergence performance in terms of convergence speed and residual error. Simulation results show that the proposed blind DFE performs much better than the blind DFE with the slicer.