• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2291-2293
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• 2011

In this paper, the composes with digital position with a computer logical operation order with the signal processing method which is pliability and result of the logical operation which confronts in input signal from the outside input-output Channel leads and about the drive which the possibility to output at the outside is a research. This Decoder IC Multiplexer & De-multiplexer, position the function with from the digital signal circle where the imagination embodiments and BIT outputs of IC etc. are possible is possible in basic and usefully from the general industrial, could be used.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.26-28
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• 2004

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.92-102
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• 1986

In this paper, Modular cell approach was applied to custom IC design or RS decoder. For the design of RS decoder by modular cells, 3 basic cells and one extra circuit are designed, these are, SYN cell for syndrome calculation, AL cell for error locator polynomial calculation, and REM cell for remaining error transform calculation. RS decoder design by these basic cells is very simple and regular, and naturally suitable for VLSI RS decoder design.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.101-106
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• 1997

Palplus system is a new European 16:9 wide screen TV format which has a full compatibility with standard PAL and the system has a advantage of improving picture quality by the reduction of cross color and cross luminance as well as making use of the full horizontal luminance bandwidth of the PAL system. We implemented European 16:9 PALplus Digital decoder(625/50/2:1) system using SVP(Serial Video Processor) IC and discrete helper demodulator.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.1
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• pp.65-74
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• 1989

This paperr presetns the Direct Decoding Method for binary BCH codes which can find the error locattion number directly from the syndrome without calculating the error locator polynomical. Also in this paper, the triple and quadruple error correcting BCH decoder are designed using this method. As an example, the triple error correcting (63.45) BCH decoder is implemented with TTL ICs. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.221-227
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• 2014

In this paper, we propose a synthesis method that can effectively suppress the ambience which affects tonal components in the PS decoder. Ambience component was obtained by using decorrelation filter and the weighting of the ambience in the decoder was determined through IC parameter. However, since the parameters are extracted in the sub-band domain, a low IC value could be analyzed even if the tonal component is dominant. The quality of the output signal may be degraded. To prevent this problem, the tonality was measured in the downmixed signal and the weighting of the ambience components were adjusted appropriately according to the measured tonality index. The performance of the proposed method was evaluated by simulations. Furthermore, the subjective test was performed and the results confirmed that the proposed method offers improved quality.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.385-392
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• 2009

Simplified minimum mean square error (MMSE) detection technique combined with soft interference cancellation(SoIC) is proposed for iterative receivers in multiple antenna systems. To avoid repeated matrix inversions required to obtain the MMSE filter coefficients during the iteration between the soft detector and decoder, simplified matrix inversion techniques are applied to calculate the filter coefficient matrix. Simulation results show that the proposed MMSE detections with SoIC indicate a comparable or slightly degraded detection performance while achieving a significantly reduced complexity as compared to the conventional MMSE detection with SoIC.