• Title/Summary/Keyword: Decimation

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A Study on Kuma Kengo's Architecture Works on Circularity - Based on Connectivity with Japanese Metabolism Movement's Circularity - (쿠마 켄고 건축의 순환성에 관한 연구 - 일본 메타볼리즘 운동의 순환성과 연계를 중심으로 -)

  • Lee, Jae-Won;Lim, Ki-Taek
    • Journal of the Regional Association of Architectural Institute of Korea
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    • v.20 no.6
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    • pp.9-16
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    • 2018
  • The purpose of this research was influenced by the historical background of Japanese modern architecture by the circulation of Kuma Kengo's architectural works and he wanted to look at the values and directions he was pursuing and how they were expressed in his works. The results of the review are summarized as follows. First, metabolism was developed as a reaction of modernism in modern architecture, focusing on growth through infinite reproduction by looking at architecture and cities as organisms and by using unit space as cells. Kuma Kengo, on the other hand, argues that focusing on the possibility of decimation of unit members by sequencing the elements that make up the space smaller than the unit space is closer to an ecological architecture. Second, what Kuma Kengo says is "erase the architecture" that is naturally related to the environment and disappears when its use is exhausted. His argument is expressed in individual architectural works through 'visual erase', 'particle painting of materials' and 'independence through dependency.' Through this, Kuma Kengo's ecological architectural languages were influenced by the ecological causes of metabolism, but they differed from the perspective of seeing architectural circulation as an organism. If metabolism was intended to realize circulation with growth potential based on the module of unit space, Kuma Kengo sought to implement circulation with the extinction of the unit members of space.

Development of a Digital Receiver for Detecting Radar Signals (레이더 신호 탐지용 디지털수신기 개발)

  • Cha, Minyeon;Choi, Hyeokjae;Kim, Sunghoon;Moon, Byungjin;Kim, Jaeyun;Lee, Jonghyun
    • Journal of the Korea Institute of Military Science and Technology
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    • v.22 no.3
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    • pp.332-340
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    • 2019
  • Electronic warfare systems are needed to be advantageous in the modern war. Many radar threat signals with various frequency spectrums and complicated techniques exist. For detecting the threats, a receiver with wide and narrow-band digital processing is needed. To process a wide-band searching mode, a polyphase filter bank has become the architecture of choice to efficiently detect threats. A polyphase N-path filter aligns the re-sampled time series in each path, and a discrete Fourier transform aligns phase and separates the sub-channel baseband aliases. Multiple threats and CW are detected or rejected when the signals are received in different sub-channels. And also, to process a narrow-band precision mode, a direct down converter is needed to reduce aliasing by using a decimation filter. These digital logics are designed in a FPGA. This paper shows how to design and develop a wide and narrow-band digital receiver that is capable to detect the threats.

Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

  • Joshi, Alok;Gupta, Dewansh Aditya;Jaipuriyar, Pravriti
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.670-681
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    • 2019
  • Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

Implementation of Real-time Stereo Frequency Demodulator Using RTL-SDR (RTL-SDR을 이용한 스테레오 주파수 변조 방송의 실시간 수신기 구현)

  • Kim, Young-Ju
    • Journal of Broadcast Engineering
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    • v.24 no.3
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    • pp.485-494
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    • 2019
  • A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.

Design and Performance Analysis of Adaptive First-Order Decimator Using Local Intelligibility (국부 가해성을 이용한 적응형 선형 축소기의 설계 및 성능 분석)

  • Kwak, No-Yoon
    • Journal of Digital Contents Society
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    • v.9 no.1
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    • pp.17-26
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    • 2008
  • This paper has for its object to propose AFOD(Adaptive First-Order Decimator) which sets a value of decimated element as an average of a value of neighbor intelligible component and a output value of FOD(First-Order Decimator) for the target pixel, and to analyze its performance in terms of subjective image quality and hardware complexity. In the proposed AFOD, a target pixel located at the center of sliding window is selected first, then the gradient amplitudes of its right neighbor pixel and its lower neighbor pixel are calculated using first order derivative operator respectively. Secondly, each gradient amplitude is divided by the summation result of two gradient amplitudes to generate each local intelligible weight. Next, a value of neighbor intelligible component is defined by adding a value of the right neighbor pixel times its local intelligible weight to a value of the lower neighbor pixel times its intelligible weight. Since the proposed method adaptively reflects neighbor intelligible informations of neighbor pixels on the decimated element according to each local intelligible weight, it can effectively suppress the blurring effect being the demerit of FOD. It also possesses the advantages that it can keep the merits of FOD with the good results on average but also lower computational cost.

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A Constant Pitch Based Time Alignment for Power Analysis with Random Clock Power Trace (전력분석 공격에서 랜덤클럭 전력신호에 대한 일정피치 기반의 시간적 정렬 방법)

  • Park, Young-Goo;Lee, Hoon-Jae;Moon, Sang-Jae
    • The KIPS Transactions:PartC
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    • v.18C no.1
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    • pp.7-14
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    • 2011
  • Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

Wavelet Transform Based Low Pass Filters and Interpolation Filters in Digital Image Communication Systems (디지털 영상 통신 시스템에서 웨이블릿 변환 기반 저역 필터와 보간 필터)

  • Yoo Hoon
    • Journal of Korea Multimedia Society
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    • v.9 no.4
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    • pp.443-450
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    • 2006
  • In digital image communication systems, YUV 4:2:0 or YUV 4:2:2 images filtered and subsampled versions of YUV 4:4:4 images are utilized and these images recover their size by an interpolation filter. Low pass filters and interpolation filters in the image communication systems are generally utilized. Thus, to improve the image quality, efficient low pass filters and interpolation filters are still required. In this paper, we propose new and efficient low pass filters and interpolation filters and their design method. The low pass filters and interpolation filters used in the MPEG-2 system were developed independently. We utilize wavelet transforms to jointly design low pass filters and interpolation filters. Simulation results show that the proposed filters are superior to the filters used in MPEG-2 in terms of PSNR. In addition, the length of the proposed interpolation filters is shorter than that of the filters used in the MPEG 2 system.

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An Automatic Extraction Algorithm of Structure Boundary from Terrestrial LIDAR Data (지상라이다 데이터를 이용한 구조물 윤곽선 자동 추출 알고리즘 연구)

  • Roh, Yi-Ju;Kim, Nam-Woon;Yun, Kee-Bang;Jung, Kyeong-Hoon;Kang, Dong-Wook;Kim, Ki-Doo
    • 전자공학회논문지 IE
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    • v.46 no.1
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    • pp.7-15
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    • 2009
  • In this paper, automatic structure boundary extraction is proposed using terrestrial LIDAR (Light Detection And Ranging) in 3-dimensional data. This paper describes an algorithm which does not use pictures and pre-processing. In this algorithm, an efficient decimation method is proposed, considering the size of object, the amount of LIDAR data, etc. From these decimated data, object points and non-object points are distinguished using distance information which is a major features of LIDAR. After that, large and small values are extracted using local variations, which can be candidate for boundary. Finally, a boundary line is drawn based on the boundary point candidates. In this way, the approximate boundary of the object is extracted.

Implementation of Precise Level Measurement Device using Zoom FFT (Zoom FFT를 이용한 정밀 레벨 측정 장치의 구현)

  • Ji, Suk-Joon;Lee, John-Tark
    • Journal of Advanced Marine Engineering and Technology
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    • v.36 no.4
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    • pp.504-511
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    • 2012
  • In this paper, level instrument is implemented using beat frequency for distance measurement which means the difference between Tx and Rx signal frequency from FMCW Radar Level Transmitter. Beat frequency is analyzed through Fast Fourier Transform of which frequency precision can be improved by applying Zoom FFT. Distance precision is improved from 146.5[mm] to 5[mm] using the advantage of Zoom FFT which can raise the frequency precision without changing the sampling frequency or FFT point number to be fixed in the beginning of designing signal processing. Also, measurement error can be reduced within 2[mm] by incresing the FFT points using the method of Spline interpolation. For verifying the effectiveness of this Zoom FFT to FMCW Radar Level Transmitter, test bench is made to measure the distance for every 1[mm] between 700[mm] and 2000[mm] and measurement error can be checked in the range of ${\pm}2$[mm].

Design and Fabrication of a Processing Element for 2-D Systolic FFT Array (고속 퓨리어변환용 2차원 시스토릭 어레이를 위한 처리요소의 설계 및 제작)

  • Lee, Moon-Key;Shin, Kyung-Wook;Choi, Byeong-Yoon;,
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.3
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    • pp.108-115
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    • 1990
  • This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

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