• 제목/요약/키워드: Dealy

검색결과 24건 처리시간 0.028초

심전도 신호의 위상학적 팹핑을 이용한 실시간 QRS 검출 알고리즘 (A real-time QRS complex detection algorithm using topological mapping in ECG signals)

  • 이정환;정기삼;이병채;이명호
    • 전자공학회논문지S
    • /
    • 제35S권5호
    • /
    • pp.48-58
    • /
    • 1998
  • In this paper, we proposed a new algorithm using characteristics of th ereconstructed phase trajectory by topological mapping developed for a real-tiem detection of the QRS complexes of ECG signals. Using fill-factor algorithm and mutual information algorithm which are in genral used to find out the chaotic characteristics of sampled signals, we inferred the proper mapping parameter, time delay, in ECG signals and investigated QRS detection rates with varying time delay in QRS complex detection. And we compared experimental time dealy with the theoretical one. As a result, it shows that the experimental time dealy which is proper in topological mapping from ECG signals is 20ms and theoretical time delays of fill-factor algorithm and mutual information algorithm are 20.+-.0.76ms and 28.+-.3.51ms, respectively. From these results, we could easily infer that the fill-factor algorithm in topological mapping from one-dimensional sampled ECG signals to two-dimensional vectors, is a useful algorithm for the detemination of the proper ECG signals to two-dimensional vectors, is a useful algorithm for the detemination of the proper time delay. Also with the proposed algorithm which is very simple and robust to low-frequency noise as like baseline wandering, we could detect QRS complex in real-time by simplifying preprocessing stages. For the evaluation, we implemented the proposed algorithm in C-language and applied the MIT/BIH arrhythmia database of 48 patients. The proposed algorithm provides a good performance, a 99.58% detection rate.

  • PDF

ATM망에서 지연과 손실을 고려한 효율적인 버퍼관리기법 (Buffer Management Mechanism Of Considering Dealy and Loss On the ATM)

  • 강현철;곽지영;강민규;남지승
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
    • /
    • pp.145-148
    • /
    • 2000
  • ATM network is considered as best suitable technology for multimedia service in various aspects such as bandwidth, capability of traffic expandability and so on. In this paper, we suggested a buffer management algorithm in ATM network to improve overall network performance with threshold and auxiliary buffer whose input consists of superpositiI on of voice and multimedia data traffic. To evaluate the proposed buffer management algorithm simulations are executed with four priorities, that is delay and loss priorities and the results are proved that network throughput is improved better than the existing partial buffer method.

  • PDF

부지연 회로를 내장한 200MHz 고속 16M SDRAM (A 200MHz high speed 16M SDRAM with negative delay circuit)

  • 김창선;장성진;김태훈;이재구;박진석;정웅식;전영현
    • 전자공학회논문지C
    • /
    • 제34C권4호
    • /
    • pp.16-25
    • /
    • 1997
  • This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

  • PDF

GPC 기법을 이용한 자기동조 PID 제어기 설계

  • 윤강섭;이만형
    • 한국정밀공학회:학술대회논문집
    • /
    • 한국정밀공학회 1995년도 춘계학술대회 논문집
    • /
    • pp.326-329
    • /
    • 1995
  • PID control has been widely used for real control system Further, there are muchreasearches on control schemes of tuning PID gains. However, there is no results for discrete-time systems with unknown time-dealy and unknown system parameters. On the other hand, Generalized predictive control has been reported as a useful self-tuning control technique for systems with unknown time-delay. So, in this study, based on minimization of a GPC criterion, we present a self-tuning PID control algorithm for unknown parameters and unknown tiem-delay system. A numerical simulation was presented to illuatrate the effectiveness of this method.

  • PDF

P2P 라이브 스트리밍에서 효율적인 부모선택 기법 (An Efficient Parent Node Selecting Mechanism on P2P Live Streaming)

  • 홍승길;박승철
    • 한국정보통신학회:학술대회논문집
    • /
    • 한국정보통신학회 2012년도 춘계학술대회
    • /
    • pp.146-148
    • /
    • 2012
  • 오늘날 P2P 라이브 스트리밍 서비스에 대한 연구가 활발히 이뤄지고 있다. 라이브 스트리밍 서비스는 실시간성에 따라 시간적절성을 보장할 수 있어야 한다. 본 논문에서는 P2P 라이브 스트리밍 서비스에 참여하는 노드의 ISP정보와 지역정보를 활용하여, 부모노드탐색의 비용을 줄이면서 부모노드와의 지연시간을 측정할 수 있는 기법을 제안한다.

  • PDF

개폐식 3방향 전자밸브의 펄스폭 변조 구동에 의한 압력제어 특성에 관한 연구 (A Study on the Pressure Control Characteristics of ON/OFF 3-way Solenoid Valve Driven by PWM Signal)

  • 정헌술
    • 대한기계학회논문집A
    • /
    • 제21권3호
    • /
    • pp.485-501
    • /
    • 1997
  • Pressure control is possible driving a simple ON/OFF 3-way valve of hydraulic servo system by pulse width modulation signal. But the pressure varies according to the duty ratio and carrier frequency and repeated on-off action induces pressure fluctuation. So equations for mean pressure and ripple amplitude are theoretically derived as a function of on/off time, the system parameters which decide the pressure characteristics are arranged and they are verified by experimental study. As the result selection criteria for the major design parameters are established and the basic strategy to suppress the unnecessary fluctuation can be provided for a hydraulic pressure control system using these type of valves.

어레이 접지전압 조정에 의한 저전력, 고성능 내장형 SRAM 회로 기술 (Low power-high performance embedded SRAM circuit techniques with enhanced array ground potential)

  • 정경아;손일헌
    • 전자공학회논문지C
    • /
    • 제35C권2호
    • /
    • pp.36-47
    • /
    • 1998
  • Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

  • PDF

Structural Characterization of Hordeum vulgare L. Chloroplast by Ozone

  • Chung, Hwa-Sook;Lim, Young-Jin;Park, Kang-Eun
    • Environmental Sciences Bulletin of The Korean Environmental Sciences Society
    • /
    • 제4권2호
    • /
    • pp.85-94
    • /
    • 2000
  • The effects of ozone on chloroplast development in barley seedlings during greening was investigated based on ultrastructural changes in the chloroplasts and band pattern changes in the chloroplast thylakoid membrane proteins. In this analysis of the chloroplast thylakoid membrane thylakoid protein band pattern by SDS-PAGE, none of the 24-hour greening bands included were clearer than the control. This means that the ozone treatment produced a dealy in chloroplast development and decreased the amount of thylakoid membrane proteins. LHC II chloroplast band of developing barley seedlings treated with 0.5 and 1.0 ppm ozone during the last 4 hours of the 24-hour greening period was weaker than the other bands. This result indicates that ozone affects the LHC II protein complex of the chloroplast thylakoid membrane. When investigating the ultastructural changes in ozone-treated chloroplast, the main site affected by 0.5 ppm ozone was the chloroplast grana, thereby explaining the delayed chloroplast development during the early phase of greening. In addition, there was also a structural change in the stromal grana of the ozone treated chloroplast during the middle phase of greening. The effects of ozone on the chloroplast of barley seedlings during the last phase of 48-hour greening were more functionally inhibiting than structural changes.

  • PDF

개인용 컴퓨터를 이용한 비선형 제어 시스템의 해석 및 설계에 관한 연구 (A Study on the Analysis and Design of Nonlinear Control Systems using Personal Computer)

  • 남문현;정철
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
    • /
    • pp.82-85
    • /
    • 1987
  • The objective of this paper is to develop computer programs to aid in the design and analysis of control systems in which nonlinear characteristics exist. Control systems are dynamic systems, which can be described using various mathematical models. A convenient model for digital computer simulation is the state model in which described using a set of linear and non linear first order differential equations. The digital simulation was performed on a IBM PC/XT personal computer, and the computer language was BASIC. There are four possible configurations from which a user may choose. When running a program, the user is asked to enter the system parameters according to a specified control system configurations are; 1. A control system with a nonlinear element followed by a plant in a feedback configurations(NLSVF1). 2. A control system with a nonlinear device situated between two plants in a feedback configurations(NLSVF2). 3. A control system with a nonlinear element followed by a plant, followed by a the dealy in feedback configurations(TLAG). 4. A motor and load with a backlash nonlinearity between dynamic portions of the motor/load configurations (BACKLASH). The matrix from state equations are integrated using combination the trapezoidal method and fixed point iteration. Several cases which have nonlinearity were implemented on the computer and the results were discussed.

  • PDF

디지털 동기좌표계 전류제어기에서의 시지연을 고려한 PWM 기법 (A Compensation Method for Time Dealy of Full Digital Synchronous Frame Current Regulator of PWM ac Drives)

  • 배본호;설승기
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
    • /
    • pp.244-246
    • /
    • 2001
  • In a full digital implementation of a current regulator, the voltage output is inevitably delayed due to arithmetic calculation and PWM. In case of the synchronous frame current regulator, the time delay is accompanied by the rotation of frame. In some applications in which the ratio of sampling frequency to output frequency is not high enough, such as high power drive or super high-speed drive, it is known that the effect of rotation of frame during the delay time causes phase and magnitude error in the voltage output. The error degrades the dynamic performance and can bring about the instability of current regulator at high speed. It is also intuitively known that advancing the phase of voltage output can mitigate the instability. In this paper, the instability problems are studied analytically and a compensation method for the error has been proposed. By means of computer simulation and complex root locus analysis, comparative study with conventional methods is carried out and the effectiveness of proposed method is verified.

  • PDF