• Journal of Software Engineering Society
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• v.24 no.2
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• pp.47-54
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• 2011

Recently, smart phones are widely used and as the phone sensors are evolved, we can get more various kinds of data from them. Using the data, many researchers take an effort to aware user's situation and the context-awareness for smart phones are actively applied to the real-world applications. However, to make an advanced information from sensing data need complex processing and analyzing information. Some of these computing processes are fully handled on smart phone or some data are processed by transferring to server. In this paper, we proposed a method for reducing user's context data generated on smart phone and designed a context generator. As a result, we can reduce a transmission data size and save a communication cost.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.170-178
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• 2005

The video data corrupted by the transmission error due to packet loss induce error propagation in decoded video data, and cause poor video quality. To remedy these corrupted video data, there have been introduced two types of error concealment techniques: spatial or temporal error concealment algorithm. Computational overhead by using spatial error concealment algorithm is a serious disadvantage in mobile video data streaming environment. In this paper, we propose hybrid type error concealment technique recovering video quality of mobile device using MPEG-4 video streaming on error-prone wireless network. Our algorithm is implemented in MPEG-4 decoder. The algorithm adopts Intel Wireless MMX technology to provide high performance of portable embedded multimedia mobile device. It is proven that the proposed algorithm shows expected performance for a mobile streaming system(PDA) on IP channels. Our approach showed better processing speed and better video quality comparing with traditional error concealment algorithm.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.65-72
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• 2015

AMI / HDB-3 method used a scrambling technique is used primarily for long distance data transmission line encoding. In this paper, information communication code standard (KS X 1001; 2014 confirmation), as defined in Hangul Character Code HDLC Flag bit or character stuffing at the data link layer and physical layer with respect to the code set for Hangul AMI / HDB-3 the code set for the new system to increase the data transmission efficiency Hangul consonant and vowel tables presented in terms of scrambling. The result of the existing system and the code set ($4{\times}4$) bit source coding rules for comparing the frequency of use Hangul consonant and vowel tables and statistics showed that about 22.01% of the data processing efficiency is improved.

• The KIPS Transactions:PartC
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• v.17C no.5
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• pp.433-440
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• 2010

Energy efficiency, low latency and scalability for wireless sensor networks are important requirements, especially, the wireless sensor network consist of a large number of sensor nodes should be minimized energy consumption of each node to extend network lifetime with limited battery power. An efficient algorithm and energy management technology for minimizing the energy consumption at each sensor node is also required to improve transfer rate. Thus, this paper propose no-overlap multi-pass protocol provides for sensor data transmission in the wireless sensor network environment. The proposed scheme should minimize network overhead through reduced a sensor data translation use to searched multi-path and added the multi-path in routing table. Proposed routing protocol may minimize the energy consumption at each node, thus prolong the lifetime of the sensor network regardless of where the sink node is located outside or inside the received signal strength range. To verify propriety proposed scheme constructs sensor networks adapt to current model using the real data and evaluate consumption of total energy.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.6
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• pp.1207-1212
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• 2018

The signal intelligence (SIGINT) technology is actively used for collecting various data, in a number of fields, including a military industry. In order to collect the signal information and data and to transmit/receive the collected data efficiently, the accurate angle-of-arrival (AOA) information is required and communication disturbance from the interference or jamming signal should be minimized. In this paper, we present the structure of an adaptive beam-forming satellite system based on the planar array antenna, for collecting and transmitting/receiving the signal information and data efficiently. The presented adaptive beam-forming system consists of an antenna in the form of a planar array, an AOA estimator based on the Multiple Signal Classification (MUSIC) algorithm, an adaptive Minimum Variance Distortionless Response (MVDR) interference canceler, a signal processing and D/B unit, and a transmission beamformer based on Minimum mean Square Error (MMSE). In addition, through the computer simulation, we evaluate and analyze the performance of the proposed system.

• Journal of the Korea Society of Computer and Information
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• v.12 no.1 s.45
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• pp.155-160
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• 2007

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.177-182
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• 2008

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.9-15
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• 2006

In this paper, signal processing techniques for noncoherent impulse-radio-based UWB (IR-UWB) communication system are proposed to provide system implementation of low power consumption and low complexity. The proposed system adopts a simple modulation technique of OOK (on-oft-keying) and noncoherent signal detection based on signal amplitude. In particular, a technique of a novel high speed digital sampler using a stable, lower reference clock is developed to detect nano-second pulses and recover digital signals from the pulses. Also, a 32 bits Turyn code for data frame synchronization and a convolution code as FEC are applied, respectively. To verify the proposed signal processing techniques for low power, low complexity noncoherent IR-UWB system, the proposed signal processing technique is implemented in FPGA and then a short-range communication system for wireless transmission of high quality MP3 data is designed and tested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.812-820
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• 2006

Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.