• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.397-400
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• 2006

Recent trend on high speed packet processing for providing multiple internet services is to use network processor instead of being implemented by legacy ASIC or FPGA. Most frequently used network processor interface is the SPI4.2. This paper address the data-rate conversion interface device between SPI4.2 and SPI3/CSIX, implemented using XILINX XC2VP40 FPGA. Furthermore, we address the methodology and necessity of flow control occurred due to the data rate difference between 10Gbps and 3.2 Gbps.

• 대한임베디드공학회논문지
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• 제7권5호
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• pp.277-284
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• 2012

To meet the usage of discrete wavelet transform (DWT) on potable devices, this paper implements 2-level DWT using a reference many-core processor architecture and determine the optimal many-core processor. To explore the optimal many-core processor, we evaluate the impacts of a data-per-processing element ratio that is defined as the amount of data mapped directly to each processing element (PE) on system performance, energy efficiency, and area efficiency, respectively. This paper utilized five PE configurations (PEs=16, 64, 256, 1,024, and 4,096) that were implemented in 130nm CMOS technology with a 720MHz clock frequency. Experimental results indicated that maximum energy and area efficiencies were achieved at PEs=1,024. However, the system area must be limited 140mm2 and the power should not exceed 3 watts in order to implement 2-level DWT on portable devices. When we consider these restrictions, the most reasonable energy and area efficiencies were achieved at PEs=256.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.228-231
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• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.913-914
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• 2006

This paper proposes a flexible IED platform which is implemented with a network processor and a DSP. DSP algorithms are downloaded through the embedded Linux based network processor remotely from ethernet. This architecture gives the best flexibility to adaptively accommodate the various algorithms needed in the IED environment. The developed IED platform can simultaneously measure data of the maximum of forty channels. The developed IED platform shows the successful operation, which measures and transfers the 8 channels data of 16bit samples sampled at 3.84kHz per each channel. The detailed performance analysis of the developed IED platform shows the about 10% processing load of CPU running at 533MHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.646-647
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• 2007

The topology processor uses the status of circuit breakers as input. It operates on the bus section connectivity data, which is stored in the data base, to determine the bus/branch topology of the network. This output of the topology processor forms part of the input to the state estimation or dispatcher power flow. This paper describes the development of the topology processor using matrix structure.

• 품질경영학회지
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• 제24권1호
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• pp.61-72
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• 1996

It is very important to determine the likelihood ratios and the prior odds for designing a Bayesian processor in Built-In-Test system. Using traditional statistics, it is not difficult to determine the initial prior odds from the field data. For a newly designed system, development testing data or laboratory testing data could be used to replace field data. The likelihood ratios which playa key role in the Bayesian processor must be carefully determined, based on laboratory testing and statistical techniques. In this paper, expressing and determining the likelihood ratios by Geometric areas, Test, and Analytical method will be presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.1105-1108
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• 1999

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image- processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. Combining several instructions to load a pixel-data from an external memory to a register, the proposed instruction reduces code size so that satisfy hish performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.635-638
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• 2002

In this paper, the connection device of RS232C and TCP/IP implementation using ARM processor and LINUX is proposed. Data interaction flash memory the multiple serial ports are transferred to ARM processor and the data are processed and formed into data packet for transfer via internet protocol. Packet flash memory Internet is decoded to extract the serial port data. The serial ports supports RS232C asynchronous protocol communication and control program is developed in GNU-C and installed in the on-board memory for packet conversion and control. The research result can be applied to terminal server, printer server and multiple serial ports equipments.