• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• The Journal of the Acoustical Society of Korea
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• v.16 no.2
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• pp.80-88
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• 1997

In this paper, the implementation of audio/data processor using ETRI DSP to support analog mode in digital/analog dual mode mobile phone is presented. Audio/data processor performs the wideband data processing, audio signal processing, demodulation function, and data rate conversion when it is operated in analog mode. These functions are programmed in assembly language, and then loaded to ETRI DSP together with vocoder program for the digital mode operation. This is a very efficient implementation of the dual mode cellular phone ASIC since the vocoder for the digital mode and audio/data processor for the analog mode are programmed together in the same hardware.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 1998.10a
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• pp.176-179
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• 1998

In structural analysis using FEM or BEM, pre_ and post_processor is necessary pre_ and post_processor and analyzer use same structural model. But many other tasks related to structural design, such as optimization, design of layout, etc, do not share that model in spite of their resemblance of requiring data. So, a pre_ and post_ processor was developed using a relational database managing system. Developed system uses the DBMS as a data storage and interacts with it using SQL interface. In this way, many other tasks that uses same structural data can be developed.

• Magazine of the Korean Society of Agricultural Engineers
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• v.39 no.1
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• pp.41-47
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• 1997

A geographical resource analysis support system (GRASS) was incorporated to an input and output processor for the agricultural nonpoint source pollution (AGNPS) model. The resulting interface system, GIS-AGNPS was a user-friendly, menu-driven system. GIS-AGNPS was developed to automatically process the input and output data from GIS-based data using GRASS and Motif routines. GIS-AGNPS was consisted of GISAGIN which was an input processor for the AGNPS model, GISAGOUT a output processor for the AGNPS and management submodel. The system defines an input data set for AGNPS from attributes of basic and thematic maps. It also provides with editing modes so that users can adjust and detail the values for selected input parameters, if needed. The post-processor at the system displays graphically the outputs from AGNPS, which may he used to identify areas significantly contributing nonpoint source pollution loads.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.3
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• pp.53-58
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• 2006

This study deals with the method of post-processing in the automatic tool path generation for 5-axis NC machining. The 5-axis NC machining cannot only cope with the manufacturing of complicated shapes, but also offers numerous advantages such as reasonable tool employment, great reduction of set-up process and so on. Thus 5-axis NC machining has been used for aircraft parts, mold and die as well as for complicated shapes such as impeller, propeller and rotor. However, most of the present CAM systems for 5-axis NC machining have limited functions in terms of tool collision, machine limits and post-processing. Especially 5-axis machine configurations are various according to the method which the rotational axes are adapted with the table and spindle. For that reason, In many cases the optimal numerical control (NC) data cannot be obtained or considerable time is consumed. To solve this problem, we applied a general post-processor for 5-axis NC machining. The validity of this post-processor should be experimentally confirmed by successfully milling to a helix shaped workpiece.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.370-374
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• 2005

This study deals with the method of post-processing in the automatic tool path generation for 5-axis NC machining. The 5-axis NC machining cannot only cope with the manufacturing of complicated shapes, but also offers numerous advantages such as reasonable tool employment, great reduction of set-up process and so on. Thus 5-axis NC machining has been used fur aircraft parts, mold and die as well as for complicated shapes such as impeller, propeller and rotor. However, most of the present CAM systems for 5-axis NC machining have limited functions in terms of tool collision, machine limits and post-processing. Especially 5-axis machine configurations are various according to the method which the rotational axes are adapted with the table and spindle. For that reason, in many cases the optimal numerical control (NC) data cannot be obtained or considerable time is consumed. To solve this problem, we applied a general post-processor fur 5-axis NC machining. The validity of this post-processor should be experimentally confirmed by successfully milling to a helix shaped workpiece.