• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.66-76
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• 2000

This paper describes design and implementation of caption-processing ASIC(Application Specific Integrated Circuits) for OSD(On Screen Display) of karaoke system. The OSD of conventional karaoke system was implemented by a general purpose DSP, however this paper suggest a design to save hardware resources. The ASIC receives commands and data of graphic and caption from host processor, and then modifies the data to have various graphic effects. The design has been done by schematic and VHDL coding. The design was verified by logic simulation and FPGA emulation on the real system. The chip was fabricated with 0.8${\mu}{\textrm}{m}$ CMOS SOG, and worked properly at the karaoke system.

• Management & Information Systems Review
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• v.4
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• pp.257-284
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• 2000

According as the drivers increase who have their cars, the comprehensive studies on the automobile for the traffic safety have been raised as the important problems. Visual Recognition System for radio-controled driving is a part of the sensor processor of Unmanned Autonomous Vehicle System. When a driver drives his car on an unknown highway or general road, it produces a model from the successively inputted road traffic information. The suggested Recognition System of the Road Traffic Safety Information Board is to recognize and distinguish automatically a Road Traffic Safety Information Board as one of road traffic information. The whole processes of Recognition System of the Road Traffic Safety Information Board suggested in this study are as follows. We took the photographs of Road Traffic Safety Information Board with a digital camera in order to get an image and normalize bitmap image file with a size of $200{\times}200$ byte with Photo Shop 5.0. The existing True Color is made up the color data of sixteen million kinds. We changed it with 256 Color, because it has large capacity, and spend much time on calculating. We have practiced works of 30 times with erosion and dilation algorithm to remove unnecessary images. We drawing out original image with the Region Splitting Technique as a kind of segmentation. We made three kinds of grouping(Attention Information Board, Prohibit Information Board, and Introduction Information Board) by RYB( Red, Yellow, Blue) color segmentation. We minimized the image size of board, direction, and the influence of rounding. We also minimized the Influence according to position. and the brightness of light and darkness with Eigen Vector and Eigen Value. The data sampling this feature value appeared after building the learning Code Book Database. The suggested Recognition System of the Road Traffic Safety Information Board firstly distinguished three kinds of groups in the database of learning Code Book, and suggested in order to recognize after comparing and judging the board want to recognize within the same group with Nearest Neighborhood Decision Making.

• Journal of Ocean Engineering and Technology
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• v.26 no.5
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• pp.63-72
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• 2012

The product lifecycle of a marine vessel can be classified into the design-production, operation-maintenance, and disposal phases. During the operation and maintenance phase, status data should be gathered from the major machinery and instruments installed on the marine vessel in order to perform efficient maintenance work. Although a PLM (product lifecycle management) system can manage the product information during the design and assembly stage, a PLM based on asset management technology is more appropriate for product information management during the operation stage. Product embedded information devices (PEIDs) are suggested for gathering real-time maintenance information during the operation and maintenance lifecycle. A PEID allows PLM to provide the capability of offering active information exchange between the lifecycle management system and equipment. This study designed a PEID to effectively obtain information and interact with a PLM system. It consists of sensors, wireless communication, and a micro-processor, which allow it to accumulate status data on the PLM system. The embedded information device and PLM enable the seamless information flow, tracking, and updating of MRO (maintenance repair and overhaul) information for a product throughout the middle of the product lifecycle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.2
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• pp.102-110
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• 2009

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1877-1884
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• 2014

Because of the limited power resource, we need a reliable low-power media access control technique suitable for unmaned remote sensor operation condition for the unmanned sensor processor to perform the task in the remote wireless network situation. Therefore CSMA/CA and X-MAC is generally considered to effectively transmit the signal in the low-power wireless network. In this paper, we propose the more efficient low-power LP-MAC Technique which consumes the minimum power and transmits the data faster in condition that the mobile nodes' joining to and leaving from the network which consists of the fixed nodes is fluid. The fixed nodes operate in an asynchronous mode to perform the network self-configuration and transmit data faster to the mobile node which is frequently join and leave the network. When the mobile node leaves the network, the network's operation mode will be synchronous mode to achieve the minimum power consumption, thus the minimum power operation becomes possible.

• The Transactions of the Korea Information Processing Society
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• v.4 no.10
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• pp.2581-2595
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• 1997

In this paper, the real-time facility of the operating system for a VOD(Video On Demand) server have been analyzed and implemented. The requirements of the real-time scheduling have been gathered by analyzing the model of the video-data-transfer-path. Particularly, the influence of the bottleneck subsystem have been analyzed. Thus, we have implemented the real-time scheduler and primitives which is proper for processing the digital video. In performance measurements, the degree of the guarantee of the real-time scheduler have been experimented. The measured data show that the most time constraints of the process is satisfied. But, the network protocol processing by the interrupt is a major obstacle of the real-time scheduling. We also have compared the difference between the real-time scheduler and the non-real-time scheduler by measuring the inter-execution time. According to the measured results, the real-time scheduler should be used for efficient video service because the processor time allocated to the process can't be estimated when the non-real-time scheduler is used.

• Korean Journal of Remote Sensing
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• v.25 no.6
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• pp.547-557
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• 2009

LIDAR (LIght Detection And Ranging) is an active remote sensing technology which provides 3D coordinates of the Earth's surface by performing range measurements from the sensor. Early small footprint LIDAR systems recorded multiple discrete returns from the back-scattered energy. Recent advances in LIDAR hardware now make it possible to record full digital waveforms of the returned energy. LIDAR waveform decomposition involves separating the return waveform into a mixture of components which are then used to characterize the original data. The most common statistical mixture model used for this process is the Gaussian mixture. Waveform decomposition plays an important role in LIDAR waveform processing, since the resulting components are expected to represent reflection surfaces within waveform footprints. Hence the decomposition results ultimately affect the interpretation of LIDAR waveform data. Computational requirements in the waveform decomposition process result from two factors; (1) estimation of the number of components in a mixture and the resulting parameter estimates, which are inter-related and cannot be solved separately, and (2) parameter optimization does not have a closed form solution, and thus needs to be solved iteratively. The current state-of-the-art airborne LIDAR system acquires more than 50,000 waveforms per second, so decomposing the enormous number of waveforms is challenging using traditional single processor architecture. To tackle this issue, four parallel LIDAR waveform decomposition algorithms with different work load balancing schemes - (1) no weighting, (2) a decomposition results-based linear weighting, (3) a decomposition results-based squared weighting, and (4) a decomposition time-based linear weighting - were developed and tested with varying number of processors (8-256). The results were compared in terms of efficiency. Overall, the decomposition time-based linear weighting work load balancing approach yielded the best performance among four approaches.